Violation Of Timing Constraints Research Articles

Evaluation of a Volume-Averaged Species Transport Model with Micro-Macro Coupling for Breakthrough Curve Prediction.

In porous water filters, the transport and entrapment of contaminants can be modeled as a classic mass transport problem, which employs the conventional convection-dispersion equation to predict the transport of species existing in trace amounts. Using the volume-averaging method (VAM), the upscaling has revealed two possible macroscopic equations for predicting contaminant concentrations in the filters. The first equation is the classical convection-dispersion equation, which incorporates a total dispersion tensor. The second equation involves an additional transport coefficient, identified as the adsorption-induced vector. In this study, the aforementioned equations were solved in 1D for column tests using 3D unit cells. The simulated breakthrough curves (BTCs), using the proposed micro-macro-coupling-based VAM model, are compared with the direct numerical simulation (DNS) results based on BCC-type unit cells arranged one-after-another in a daisy chain manner, as well as with three previously reported experimental works, in which the functionalized zeolite and zero-valent iron fillings were used as an adsorbent to remove phosphorous and arsenic from water, respectively. The disagreement of VAM BTC predictions with DNS and experimental results reveals the need for an alternative closure formulation in VAM. Detailed investigations reveal time constraint violations in all the three cases, suggesting this as the main cause of VAM's failure.

Evolving scheduling heuristics with genetic programming for optimization of quality of service in weakly hard real-time systems

The weakly hard real-time system model is used for describing the real-time systems that allow occasional violations of real-time timing constraints. These systems include real-time control systems, multimedia systems, and communication systems. In some approaches that deal with mitigating the system overload in real-time systems with periodic tasks, namely job-skipping algorithms, the constraints defined by the weakly hard real-time model are used as a mechanism for defining the pattern of task instances (jobs) that may be skipped in order to reduce the system load. The performance of these algorithms is usually evaluated with respect to the quality of service metric, which depends on the number of skipped jobs. In this work, we investigate the possibility of using genetic programming in the automated synthesis of scheduling heuristics for optimizing skipping patterns in order to increase the average quality of service in comparison with the conventional job-skipping algorithms. Using genetic programming to automatically synthesize heuristics allows for an easy and quick design of novel heuristics for various problem types and optimization criteria. We present two different approaches for implementing the proposed method. The first approach is to encapsulate the evolved heuristics into job-skipping algorithms known from the literature, namely Red Tasks as Late as Possible (RLP) and Blue When Possible (BWP). The idea of the second approach is to employ the evolved heuristics as standalone job-skipping algorithms. The results show an improvement of up to 15% in comparison with the state-of-the-art algorithms. The novel methods described in this work present a significant upgrade of the standard job-skipping algorithms as they provide a notable improvement in terms of quality of service while ensuring the fulfillment of weakly hard constraints. Moreover, the presented methods are computationally efficient and are therefore suitable for implementation on real-time operating systems, which is not the case with similar methods based on optimization techniques.

Design of 64-Bit Arithmetic Logic Unit Using Improved Timing Characterization Methodology for RSFQ Cell Library

Accurate timing characterization of library cells is essential for adopting the standard digital design flow using EDA tools, such as static timing analysis (STA) with timing back-annotation. For RSFQ circuits, the propagation delay of a cell is influenced by the input and output load. We have developed an automated timing characterization methodology that facilitates extraction of timing constraints and propagation delays for each cell as a function of all the possible permutations of input and output load. While being highly accurate, such a comprehensive timing characterization requires a large number of simulation runs. To significantly reduce the total number of simulation runs, we propose to analyze independently, rather than jointly, the effect of succeeding cells with standard preceding load and preceding cells with standard succeeding load. In addition, for succeeding cells with a storage loop, the delay of a cell is dependent on the state of the succeeding cell. STA tools cannot account for state-dependent timing variations. To mitigate state-dependent timing constraint violations, a state-dependent timing correction is added to the hold/set-up time. We have generated Liberty files for multiple process corners using the load dependent as well as standard load timing tables. We compare the timing accuracy for each methodology. We have designed and simulated a 64-bit ALU with 90,256 junctions with Verilog HDL and timing back-annotation across multiple process corners using Synopsys VCS tool. To validate the three timing characterization methodologies, we have evaluated their timing accuracies by comparing with full circuit simulations on representative ALU sub-blocks.

Data analytics for time constraint adherence prediction in a semiconductor manufacturing use-case

Semiconductor manufacturing represents a challenging industrial environments, where products require more than several hundred operations, each representing the technical state-of-the-art. Products vary greatly in volume, design and required production processes and, additionally, product portfolios and technologies change rapidly. Thus, technologically restricted rapid product development, stringent quality related clean room requirements and high precision manufacturing equipment application enforce operational excellence, in particular time constraints adherence. Product specific time constraints between two or more successive process operations are an industry-specific challenge, as violations lead to additional scrapping or reworking costs. Time constraint adherence is linked to dispatching and currently manually assessed. To overcome this error-prone manual task, this article presents a data-based decision process to predict time constraint adherence in semiconductor manufacturing. Real-world historical data is analyzed and appropriate statistical models and scoring functions derived. Compared to other relevant literature regarding time constraint violations, the central contribution of this article is the design, generation and validation of a model for product quality-related time constraint adherence based on a real-world semiconductor plant.

Business process specification, verification, and deployment in a mono-cloud, multi-edge context

Despite the prevalence of cloud and edge computing, ensuring the satisfaction of time-constrained business processes, remains challenging. Indeed, some cloud/edge-based resources might not be available when needed leading to delaying the execution of these processes? tasks and/or the transfer of these processes? data. This paper presents an approach for specifying, verifying, and deploying time constrained business processes in a mono-cloud, multi-edge context. First, the specification and verification of processes happen at design-time and run-time to ensure that these processes? tasks and data are continuously placed in a way that would mitigate the violation of time constraints. This mitigation might require moving tasks and/or data from one host to another to reduce time latency, for example. A host could be either a cloud, an edge, or any. Finally, the deployment of processes using a real case-study allowed to confirm the benefits of the early specification and verification of these processes in mitigating time constraints violations.

Аналітичні моделі багатопріоритетних хмарних дата-ценрів зі змішаною дисципліною надання послуг з урахуванням особливостей функціонування та можливих відмов

One of the main indicators of the effectiveness of cloud data centers are indicators based on the assessment of temporal characteristics. Violation of permissible time constraints, for example, the response time of cloud data centers, has a negative impact on the efficiency of solving user target tasks. This is of particular importance for real-time systems and, above all, for special information systems built using private clouds. Analytical models of cloud data centers are developed as queuing systems with a mixed discipline of resource allocation. The models take into account failures and various features of functioning and have arbitrary distribution laws for some stochastic processes. For each model, analytical expressions for computing time characteristics have been obtained. Such models for the cloud data centers are used for the first time. General description of the models is as follows. At the input of the cloud date - center, which implements a mixed service discipline (with relative and absolute priorities), receives N Poisson flows of requests for resources with corresponding N priorities. Duration of service for applications of various flows have their own arbitrary distribution laws. An application with relative priority, whose service is interrupted by applications with absolute priority, returns to the queue. Two disciplines for the renewal of service A and B are considered. Within the same priority, applications are serviced in the order of receipt. Cloud the date-center refuses to provide resources (for example, fails) under the Poisson law, and is restored under an arbitrary law. During the recovery period, elements of adaptation to failures are used: applications of some flows to the queue are accepted and accumulated, while others are not accepted (the discipline of the queue replenishment, I and II, respectively). The denial of service device can occur both during its free state and during the application processing. Two disciplines of resumption of service after restoration C and D have been considered. An interrupted application is processed from the point of its interruption. The combination of disciplines — resumption of service and queue replenishment — allows us to consider independent models of various types of systems that have the respective designation. Different features of functioning consist of various combinations of disciplines A, B, C, D, I and II, for which analytical formulas for calculating time characteristics of different types of systems have been obtained.

FPGA-Centric Design Process for Avionic Simulation and Test

Real-time computing systems are increasingly used in aerospace and avionic industries. In the face of power challenge, performance requirements and demands for higher flexibility, hardware designers are directed toward reconfigurable computing using field programmable gate arrays (FPGAs) that offer high computation rates per watt and adaptability to the application constraints. However, considering reconfigurable computing in the avionic design process leads to several challenges for system developers. Indeed, such technology should be validated along the verification & validation cycle starting with simulation tools, passing through the test benches and finishing with the integration phase. For each step, the FPGA can play an essential role to achieve better performances, more adaptive systems, and cost-effective solutions. In this paper, we present a seamless FPGA-centric design process for avionic equipments. Along this process, we redefine the role of the FPGA circuits to cover the simulation, the test, and the integration steps. First, reconfigurable logics are used in the frame of heterogeneous CPU/FPGA computing in order to obtain high speed-up for real-time avionic simulation. The proposed environment supports dynamic execution model enabling reconfiguration during runtime to avoid the timing constraint violation. Second, the FPGA is used as a key solution to offer versatile test benches and to converge toward unified test and simulation tools. We have designed several commercial input output intellectual property systems with dynamic runtime reconfiguration capabilities, in order to mitigate component obsolescence and to provide increased flexibility and decreased design time. Third, at the integration phase, we use the conventional tools to make profit from reconfigurable technology in embedded avionic applications in order to deliver high computation rates and to adapt their functioning mode to provide reliability, fault tolerance, deterministic timing guarantees, and energy efficiency.

Electromagnetic fault injection: the curse of flip-flops

Electromagnetic (EM) waves have been recently pointed out as a medium for fault injection within integrated circuits (IC). Indeed, it has been experimentally demonstrated that an EM pulse (EMP), produced with a high-voltage pulse generator and an injector similar to that used to perform EM analyses, was susceptible to create faults exploitable from a cryptanalysis viewpoint. An analysis of the induced faults revealed that they originated from timing constraint violations. In this context, this paper demonstrates that EM injection, performed with enhanced injectors, can produce not only timing faults but also bit-set and bit-reset faults on an IC at rest. This first result clearly extends the range of the threats associated with EM fault injection. It then demonstrates, considering two different ICs under operation: an FPGA and a modern microcontroller, that faults produced by EMP injection are not timing faults but correspond to a different model which is presented in this paper. This model allows to explain experimental results introduced in all former communications.

Improving the State Space Computation of the Time Stream Petri Nets Model

An enumerative technique is presented allowing the reachability analysis of weakly synchronous systems modeled using time stream Petri net (TSPN). In a TSPN, time constraints are associated with incoming arcs, whereas synchronization rules are associated with transitions, thus allowing the violation of time constraints. We propose an approach to contract the TSPN state space by building its state class graph. Each class therein is a pair (M, D), where M is a marking and D is a system that can be encoded in a difference bound matrix, as long as no arc's time constraint violation is reported. Hence, each reachable class is computed by applying an optimal algorithm in a square complexity time. For this effect, efficient conditions for the consistency, firing and equivalence tests are provided to ensure a finite graph construction when the model is bounded. Finally, in order to validate our approach, experimental results are reported.

A RED modified weighted moving average for soft real-time application

Abstract The popularity of TCP/IP has resulted in an increase in usage of best-effort networks for real-time communication. Much effort has been spent to ensure quality of service for soft real-time traffic over IP networks. The Internet Engineering Task Force has proposed some architecture components, such as Active Queue Management (AQM). The paper investigates the influence of the weighted moving average on packet waiting time reduction for an AQM mechanism: the RED algorithm. The proposed method for computing the average queue length is based on a difference equation (a recursive equation). Depending on a particular optimality criterion, proper parameters of the modified weighted moving average function can be chosen. This change will allow reducing the number of violations of timing constraints and better use of this mechanism for soft real-time transmissions. The optimization problem is solved through simulations performed in OMNeT++ and later verified experimentally on a Linux implementation

A sample average approximation method for disassembly line balancing problem under uncertainty

This paper considers a Disassembly Line Balancing Problem (DLBP) under uncertainty. Disassembly task times are assumed to be random variables with known probability distributions. To deal with this uncertainty, a stochastic program is developed. It both chooses the best disassembly alternative for an end of life product and assigns the corresponding disassembly tasks to the workstations of the line with the aim to minimize the line cost. The latter includes the operation costs for workstations as well as penalty costs generated by the cycle time constraint violations. AND/OR precedence constraints among tasks are observed. A proposed solution algorithm is capable of providing high quality solutions even for large scale problem instances. It integrates Monte Carlo sampling techniques with the L-shaped algorithm.

Lagrangian relaxation and cut generation for sequence-dependent setup time flowshop scheduling problems to minimise the total weighted tardiness

The Lagrangian relaxation and cut generation technique is applied to solve sequence-dependent setup time flowshop scheduling problems to minimise the total weighted tardiness. The original problem is decomposed into individual job-level subproblems that can be effectively solved by dynamic programming. Two types of additional constraints for the violation of sequence-dependent setup time constraints are imposed on the decomposed subproblems in order to improve the lower bound. The decomposed subproblem with the additional setup time constraints on any subset of jobs is also effectively solved by a novel dynamic programming. Computational results show that the lower bound derived by the proposed method is much better than those of CPLEX and branch and bound for problem instances with 50 jobs and five stages with less computational effort.

Scheduling and control of real-time systems based on a token player approach

Petri nets are a powerful formalism for the specification and verification of concurrent systems, such as sequential systems and manufacturing systems. To deal with real-time systems whose time issues become essential, different extensions of Petri nets with time have been proposed in the literature. In this paper, a new scheduling and control technique for real-time systems modeled by ordinary P-time Petri nets is proposed. Its goal is to provide a scheduling for a particular firing sequence, without any violation of timing constraints ensuring that no deadline is missed. It is based on the firing instant notion and it consists in determining an inequality system generated for a possible evolution (in terms of a feasible firing sequence for the untimed underlying Petri net) of the model. This system can be used to check reachability problems as well as evaluating the performances of the model considered and determining the associated control for a definite functioning mode and it introduces partial order on the execution of particular events.

고신뢰성 발사통제시스템을 위한 고장허용 통신 미들웨어 설계 및 구현

발사통제시스템(Launch Control System)은 유도무기체계에서 유도탄의 발사와 관련된 일련의 절차들을 제어하는 시스템이다. 이 시스템은 지정된 시간 안에 목표물에 대한 교전계획을 생성하고 이 정보를 탄에 장입하며 탄의 발사 제어를 수행해야 한다. 이 때문에 시스템의 하드웨어, 소프트웨어 고장뿐만 아니라 정해진 수행 시간의 초과 때문에도 임무가 실패될 수 있다. 본 논문에서 제안한 것은 발사통제시스템과 같은 내장형 실시간 시스템을 위한 고장허용 이더넷으로 별도의 하드웨어나 소프트웨어 없이 기존 상용의 이더넷 디바이스를 이중화하여 네트워크에 고장허용 기능을 제공하는 방법이다. 이를 위해 시스템의 각 구성 노드들을 이중의 네트워크 채널로 중복 시키고, 네트워크 트래픽에 대한 고장탐지 및 복구를 위해 통신 미들웨어를 설계하고 개발하였다. 이중채녈 기반의 통신 미들웨어를 통해 처리 시간이 중요한 시스템에 네트워크 고장으로 인한 시스템 중지를 방지하고 노드에 통신 손실이 발생하지 않도록 하였다. Launch control system controls the sequence for launching missile in weapon systems. This system have to generate the engagement plan, input information and launch the missile in timeliness requirement. Such a system may fail to operate correctly either due to errors in hardware and software or due to violation of timing constraints. We presented fault-tolerant ethernet for embedded real-time system like launch control system. This approach is designed to handle network faults using dual commercial-off-the-shelf(COTS) network devices. To support fault-tolerant ethernet each node is composed dual channel ethernet and designed the communication middleware for network fault detect and recovery. Especially for time-critical system, the middleware is being developed to achieve that no point of network failure shall take down or cause loss of communication to network nodes.

Monitoring of Timing Constraints with Confidence Threshold Requirements

In many emerging time-critical applications, the exact time of event occurrences may not be known. In such cases, events can be represented as a probabilistic occurrence within a time interval. Thus, monitoring of timing constraints, generally used in time- critical systems, needs to incorporate the uncertainty of event occurrences. In this paper, we propose mechanisms to monitor the satisfaction/violation of timing constraints that can be assessed probabilistically. We assume a uniform distribution of event occurrence within a time interval. Our proposed algorithm determines whether the probability that a timing constraint has been satisfied exceeds a specified threshold value. A confidence threshold is a minimum satisfaction probability of the timing constraint. A timing constraint is violated if the confidence threshold is not reached. We design an efficient monitoring algorithm for detecting timing violations of a set of timing constraints by finding the earliest expiration time (EET) for each timing constraint. Since it is critical to derive implicit constraints for early detection of violation of timing constraints, we present the derivation of the implicit constraints under uncertainty using an all-pairs shortest path algorithm. Further, we propose pruning techniques to discard unnecessary implicit constraints. We present the properties and proofs of our approach.

Safe worst-case execution time analysis by abstract interpretation of executable code

To verify that a safety-critical application meets all requirements lies in the responsibility of the system designers. Classical software validation methods like code review and testing with debugging are expensive and cannot really guarantee the absence of errors. In constrast, abstract interpretation provides a methodology for static program analysis that yields statements valid for all program runs with all inputs. Employing static analyzers is thus orthogonal to classical testing. A possible cause of catastrophic failure is the violation of timing constraints. Recent trends, e.g. in automotive industries (X-by-wire, time-triggered protocols) require knowledge on the Worst-Case Execution Time (WCET) of each task. Yet WCET determination is a difficult problem because of the characteristics of modern software and hardware. This talk focuses on AbsInt's tool aiT that combines abstract interpretation and integer linear programming to determine upper bounds for the WCETs of code snippets given as routines in executables. The hardware architecture of the underlying processor is precisely taken into account, including cache and pipeline behavior. Bounds are determined without the need to change the code and hold for all executions. aiT is used among others by Airbus in the development of various safety-critical applications for the A380.

A scalable method for testing real-time systems

Real-time systems (RTSs) are used in different domains such as telephone switching systems, air traffic control systems and patient monitoring systems. The behavior of RTSs is time-sensitive; that is, RTSs interact with their environment with input and output events under time constraints. The violation of such time constraints is the main cause of the misbehavior of RTSs, and may result in severe damage to human lives and the environment [Mandrioli, D., Morasca, S., & Morzenti, A. 1995. ACM Transactions on Computer Systems, 13(4), 365---398]. To prevent failures in RTSs, we must verify that the implementation of an RTS is correct before its deployment. Testing is one of the formal techniques that can be used to achieve this goal. It consists of three main phases: test generation, test execution, and test results analysis. This paper presents a test case generation method for RTSs modeled as Timed Input Output Automata (TIOA). The approach is made in two steps. First, the TIOA describing the system being tested is sampled to construct a subautomaton, which is easily testable (i.e., easy to generate test cases from it). Then, the resulting subautomaton is traversed to generate test cases. Our method is scalable in the sense that it generates a small number of test cases even when the specifications are significant. Moreover, the test cases derived by our method are executable (i.e., they can be run on any error-free implementation of the system being tested).

Technology Related Timing Jitter in Superconducting Electronics

Digital superconducting systems based on Josephson junctions make generally use of the synchronous timing strategy. Today, one of its most promising applications is the high speed and high dynamic range signal sensing. A digital signal acquisition system should have a high resolution as well as a short sampling interval with a well known and constant time period. Short term clock fluctuations (clock jitter) induced by thermal noise can significantly disturb the system operation due to hazards of timing constraint violations. This uncertainty in the time period is currently a strong limitation for further improvements of fast signal sensing systems based on superconductive electronics. Recently, several theoretical and experimental studies describe the timing jitter in simple circuits, like Josephson transmission lines. In the presented work, we analyse different fabrication technologies for rapid single flux quantum (RSFQ) electronics and predict their timing jitter by the numerical solution of stochastic differential equations. We obtained a very good agreement between our simulation data and recent experimental results.

UML Profiles for Real-Time Systems and their Applications.

Real-time systems (RTS) have strict timing constraints and limited resources. The satisfaction of RTS timing constraints is required for their correction. In order to reduce the cost due to late discovery of design flaws and/or violations of timing constraints of RTS as well as to speed up their development to cope with time-to-market requirements, it is important to validate, at early stages of the development process, the functional and nonfunctional properties of RTS. In addition, RTS complexity is continuously increasing which makes their design very challenging. UML, a graphical object-oriented modeling language, is suitable to deal with this complexity. UML also supports predictive, quantitative analysis through its real-time profiles. The objective of this paper is to review the most important UML profiles for real-time from the academia, the industry and/or standard organizations; and the research activity that revolves around these profiles.

Short-term frequency stability of clock generators for multigigahertz rapid-single-flux quantum digital circuits

Superconducting digital systems based on Josephson junctions have generally used a synchronous timing strategy. A master clock signal is used to delimit a data window during which the system changes state and data is transferred from one block to the next. The temporal stability of the clock signal has a profound effect on the performance of rapid single flux quantum (RSFQ) digital systems. In particular, short-term clock fluctuations, or clock jitter, can degrade system performance due to the hazard of timing constraint violations. The successful development of large-scale RSFQ digital systems will require highly stable multigigahertz on-chip clock sources. To meet this need, methods for characterizing and measuring the short-term stability of such sources are required. We identify the relevant figure of merit to characterize and compare various clocks: the cycle-to-cycle standard deviation of the clock periods. We present experimental techniques for the measurement of this figure of merit and apply them to the measurement of jitter in a clock generator used often in RSFQ systems, the ring oscillator. High-frequency phase noise measurements found the jitter of a 9.6-GHz clock to be in the range from 0.6% to 0.36% of the clock period. The measured values of clock jitter fell within the 95% confidence interval of our stochastic circuit simulations. This was sufficient evidence to conclude that thermal noise from the resistors in the circuit may be the dominant source of jitter in the ring oscillator.