Video Processing Circuits Research Articles

DESIGN AND IMPLEMENTATION OF EFFICIENT DIGITAL FILTERS USING LABVIEW

In digital signal processing, the purpose of a filter is to remove unnecessary components in the signal, such as random noise. An infinite impulse response (IIR) filter is an iteration-type filter. The current pattern resulting from the IIR filter is based on the current input and output patterns. Several methods are available to detect digital IIR filters. Filters are widely used in signal processing and communication device approaches such as in channel equalization; noise reduction; radar systems; audio, speech signal, video, and biomedical signal processing, and economical, electrocardiogram, electroencephalogram, electromyography, and electrical circuit analyses. In this study, we used the Laboratory Virtual Instrument Engineering Workbench (LabVIEW) software program to analyze the design and implementation of an efficient digital filter, the results of which are presented in this paper. The important objective of this task was to design and examine different IIR filters-namely, Chebyshev, Butterworth, and Elliptic filters-using LabVIEW for the simulation processes. LabVIEW is used by graphical programming environmental engineers to implement automated research, certification, and product testing systems. In this work, the LabVIEW graphical programming tool was used because it gives accurate results in real time compared to other available simulation tools.

Design of Real Time Video Image Acquisition and Processing System Based on FPGA

Based on characteristics of instantaneously, large capacity and miniaturization of digital image acquisition and processing technology, a real-time video image acquisition and processing circuit system was designed, FPGA was used as the center of controlling the whole system and the center of processing image data. With DDR2 SDRAM the core component of high speed storage module, and CMOS 7670 the video image acquisition device. Through the Quratus II and Modelsim software for edge detection algorithm mand the control process, each module of the hardware design and simulation, the realization of the video images from the collection and storage to the treating and display, which shows smooth, clear and real-time.

TDI CCD成像电路系统响应模型的研究

To establish accurate response model of time delay integration charge coupled device (TDI CCD) image system, the main parts are analyzed in detail, such as CCD sensor, amplifier circuits and video processing circuit, according to the flow of signal processing. The response model for the actual system is established in theory based on the flow processing. The noises of dark current, video processing circuit are tested on a spatial TDI CCD image system. And so is the radiometric calibration under conditions of different parameters and illuminations. The image data of experiments is analyzed. An approximate formula and a precise formula are achieved by linear polynomial and quadratic polynomial of the least square method. The goodness of fit for linear and quadratic polynomial shows that R2 reaches 0.992 and 0.9998, respectively. The radiation character of ground targets can be acquired by the response model. And the choice of reasonable working parameter can also be decided according to the model. The experimental results show that the response model of image system is accurate and the working parameters are reasonable, which meets the demand and improves the efficiency of on-orbit spatial camera.

Teaching Design of Video Processing Circuits

Design of a video processing circuit requires extensive understanding of digital systems and image processing algorithms. A typical design process involves different tools and languages, which make the task difficult for undergraduate students. We present a teaching method using a web-based tool for initial algorithm study and test bench design. The algorithm is later described in a high-level language, optimised and implemented on a custom programmable logic platform.

Research of Circuit System in CCD Ultraviolet Sensor for Probing Moon

介绍了我国探月工程之嫦娥一号卫星的紫外CCD敏感器系统的CCD电路的软硬件的开发研究.紫外CCD敏感器由光学结构、CCD及处理线路、数据处理单元及其软件组成.入射光经光学系统后,照射在CCD敏感元件,经视频处理电路处理后形成数字图像信号.数字图像信号保存在数据存储器中,由数据处理器进行分析处理.计算得到月球的中心并转换为探测器对月姿态角,其中紫外CCD敏感器头部电路包括CCD电路、时序电路、驱动电路、视频处理电路和电源电路.核心器件CCD采用E2V公司的CCD48-20芯片,文中重点介绍该CCD的时序、驱动和Smear等难点问题.

Reconfigurable computing for shape-adaptive video processing

Various reconfigurable computing strategies are examined regarding their suitability for implementing shape-adaptive video processing algorithms of typical object-oriented multimedia applications. The utilisation of reconfigurability at different levels is investigated and the implications of designing reconfigurable shape-adaptive video processing circuits are addressed. Simple models for representing arbitrarily shaped objects and for mapping them into object-specific hardware designs are developed. Based on these models, several design and reconfiguration strategies, targeting an efficient mapping of shape-adaptive video processing tasks to a given reconfigurable computing architecture, are investigated. A number of real applications are analysed to study the trade-offs between these strategies. These include a shape-adaptive discrete cosine transform characterised by a limited number of different data-dependent computations and a shape-adaptive template matching method consisting of a virtually unlimited number of different computation possibilities. It is argued that shape-adaptive video processing algorithms with a relatively small number of different configuration contexts can often be more efficiently implemented as a static or multiconfiguration design, while a design employing dynamic or partial reconfiguration will be more suitable or even necessary if the number of different computation possibilities is relatively large.

VLSI implementations of image and video multimedia processing systems

An overview of very large scale integrated (VLSI) implementations of multimedia processing systems is given with particular emphasis on architectures for image and video processing. Alternative design approaches are discussed for dedicated image and video processing circuits and for programmable multimedia processors. Current design examples of dedicated and programmable architectures are reviewed, and the techniques employed to improve the performance for multimedia processing are therein identified. Future trends in multimedia processing systems are anticipated with respect to current developments in emerging image and video multimedia applications.

High-performance digital color video camera

Typical one-chip color cameras use analog video processing circuits. An improved digital camera architecture has been developed using a dual-slope AID conversion technique and two full-custom CMOS digital video processing integrated circuits, the color filter array (CFA) processor and the ROB postprocessor. The system uses a 768 x 484 active element interline transfer CCD with a new field-staggered 3G color filter pattern and a lenslet overlay, which doubles the sensitivity of the camera. The industrial-quality digital camera design offers improved image quality, reliability, and manufacturability, while meeting aggressive size, power, and cost constraints. The CFA processor digital VLSI chip includes color filter interpolation processing, an optical black clamp, defect correction, white balance, and gain control. The RGB postprocessor digital integrated circuit includes a color correction matrix, gamma correction, two-dimensional edge enhancement, and circuits to control the black balance, lens aperture, and focus.

Consumer electronics: The problems and promises of high-definition television: Its future looks brighter, yet challenges remain in bandwidth, standards, and compatibility

The principal barriers, such as incompatibility, to the use of high-definition television for home use are examined. A discussion is presented of the CBS system, which is compatible in the sense that a conventional receiver, with the addition of new baseband video-processing circuits, could receive the HDTV signals and display a conventional 525-line color picture. HDTV receivers, when available, could display a high-definition 1050-line picture. Scanning and transmission issues are also considered.

Television Receiver using a Pure Synchronous Detector IC

This paper describes a new excellent video detector IC for color television receivers with phase lock loop ( PLL ) operating at the intermediate frequency of 58.75 MHz generator. The IC includes IF amplifier, AGC circuit, VCO, video processing circuit, video detector, automatic phase control ( APC ) circuit, lock-unlock condition detector and AFC circuit. Using this system, better performance than a traditional diode detector or a quasi synchronous detector has been achieved with no increase of manufacturing cost.

Television Receiver Design Trends in the U.K.

In spite of the similarity in the Domestic television market U.S. and U.K. receiver designs differ appreciably. In the U.K. virtually all receivers are hybrid, valves being retained for the output circuits only. In the signal amplifying circuits transistors can give improved noise performance, particularly at U.H.F., and varicap diodes simplify the mechanical aspects of the tuner. The video and signal processing circuits are again ones that lend themselves to transistor circuitry, particularly in the case of colour receivers. The power supply for a transistor receiver imposes a cost penalty and conventional tube circuits provide the most economic solution for the scanning system. High voltage semiconductor diodes, however, can simplify the e.h.t. generator circuit in a colour receiver. The combination of transistors and tubes pose many problems to the receiver designer. One major hazard to transistors is the effect of picture tube flashover. This gives rise to excessive voltage and current transients in a receiver and protection is necessary.

The Video Processing Circuits of an all Transistor Television Receiver

This paper describes the circuits which process the detected video signal and extract from it the various sub-signals required by the receiver. The transistor requirements for these circuits are discussed and recommended transistors and circuits are shown. Performance data and design considerations are included to enable the circuit designer to choose the particular features which are applicable for his requirements.