Vias In Printed Circuit Boards Research Articles

Mode-Decomposition-Based Equivalent Model of High-Speed Vias up to 100 GHz

Via transitions in high-speed channels critically influence the signal integrity and power integrity of high-speed systems. In this work, a mode-decomposition-based equivalent model of a high-speed via that can be applied at frequencies up to 100 GHz is proposed for the first time. The equivalent model for modeling the via transition consists of upper and lower via-to-plate capacitances and equivalent parallel-plate impedances, owing to the fundamental mode and higher-order modes for parallel-plate, all of which can be calculated from physical geometrical parameters. The via-to-plate capacitances are calculated by using the domain decomposition method in the anti-pad domain and via domain. The parallel-plate impedances representing via and parallel-plate coupling are calculated with the mode decomposition method for different parallel-plate modes (fundamental and higher-order modes) in the parallel-plate domain. The proposed equivalent via model provides more accurate results in the high-frequency range than previously proposed methods. Because the impact of higher-order modes on parallel-plate impedance is considered in the proposed mode-decomposition-based via model, and the effects of higher-order modes are prominent at high frequencies for printed circuit board vias with typicaldimensions.The proposedmodel is validated with numerical examples, which show good correlation at frequencies as high as 100 GHz. The proposed model can be applied to high-speed via transitions in printed circuit boards and packages.

Thermal resistance modelling and design optimization of PCB vias

Various reference printed circuit board (PCB) thermal designs have been provided by semiconductor manufacturers and researchers. However, the recommendations are not optimal, and there are some discrepancies among them, which may confuse electrical engineers. This paper aims to develop an analytical thermal model for PCB vias, and further to find the optimal design for thermal resistance minimization. Firstly, the vertical thermal resistance of a PCB via array is analytically modelled. Then the dependence of the thermal resistance on multiple design parameters is analysed, and the optimal via diameter is found for different PCB specifications. Finally, the developed thermal model and optimal trajectory are verified by computational fluid dynamics (CFD) simulations and experiments.

Assessment of Joule Heating and Temperature Distribution on Printed Circuit Boards Via Electrothermal Simulations

A printed circuit board (PCB) comprises a solid piece of dielectric material with embedded layers of current carrying metal traces and vias. Geometric features of these metal traces and vias in modern PCBs are highly nonuniform and complicated such that the card level or system level numerical simulations by using the actual trace and via geometries are computationally expensive. The present study investigates the effects of Joule heating in current carrying traces on the temperature distribution of PCBs by conducting one-way and two-way direct current (DC) electric and computational fluid dynamics (CFD) simulations. DC electric field simulations are performed to determine the power map of trace layers which are modeled as planar heat generating sources by using the temperature-dependent electrical conductivity of the metal trace. The power distribution varies with the implemented size and power thresholds. Thermal conductivity map of the PCB is determined by using the electronic computer-aided design (ECAD) images of the individual layers. By using these planar source and thermal conductivity maps, CFD simulations are conducted to determine the resulting temperature distribution on the board. A methodology is developed and applied to a sample, complex PCB, and the generated results are compared with those of the previous studies and conventional models. The computational data show that the temperature distributions over the PCB and its mounted components experience large variations based on the implemented thermal conductivity mapping and the Joule heating modeling technique.

전해 Cu Via-Filling 도금에서 염소이온이 가속제와 억제제에 미치는 영향

Recently, the weight reduction and miniaturization of the electronics have placed great emphasis. The miniaturization of PCB (Printed Circuit Board) as main component among the electronic components has also become progressed. The use of acid copper plating process for Via-Filling effectively forms interlayer connection in build-up PCBs with high-density interconnections. However, in the case of copper-via filled in a bath, which is greatly dependent on the effects of additives. This paper discusses effects of Cl ion on the filling of PCB vias with electrodeposited copper based on both electrochemical experiment and practical observation of cross sections of vias.

Failure mechanism of solder bubbles in PCB vias during high‐temperature assembly

PurposePb‐free soldering challenged printed circuit board (PCB) assembly with high temperature. The purpose of this paper is to explain the failure mechanism of printed circuit board (PCB) assembly with solder bubbles of vias to avoid the problems of via‐drilling defects and solder joint failure.Design/methodology/approachThe failure of PCB vias with solder bubbles was investigated through cross sections and SEM microstructure inspection, TMA measurement, moisture absorption analysis and DSC measurement. The moisture absorption and CTE of FR4 laminate matched with manufacturing requirement to avoid the effects of solder bubbles. The effects of via drilling with a dull drill bit were compared to that with a new drill bit.FindingsThe moisture absorbed inside holes of via plating layers could be exposed to induce solder bubbles during Pb‐free soldering assembly and dull drill bits should be prevented during the drilling process to avoid the no‐bearing drilling effects.Originality/valueThe failure of PCB vias is not only involved in the voiding in solder joints but manufacturing processes of PCB. The paper designs an approach to analyse the properties of PCB materials and the drilling effects of vias to find out the mechanism resulting in solder bubbles of vias. The problem of drill bits should be considered to prevent the moisture absorbed in drilling vias with defects.

Failure investigation on copper-plated blind vias in PCB

Failures like open circuit are always encountered in PCBs (printed circuit boards) due to defects in the blind vias. In this paper, systematic analysis such as macro and micro observation was carried out on cracking blind vias in PCB used for mobile phones. The predominant cracking mechanism of sulfur segregation in form of Cu x S, which was generated by the excessive use of brightener additive, was proposed for the first time. Meanwhile, grain coarsening in copper deposition led by inappropriate current density was the other main cause for ductility decreasing in the plating layer. Complementarily, microcrack propagation was explained based on the finite element method (FEM) results of stress distribution after thermal cycling. Finally, suggestions and countermeasures were addressed, which were of importance for reference to the structural integrity and electrical reliability of blind vias in PCB during process and service.

Performance analysis of signal vias using virtual islands with shorting vias in multilayer PCBs

The mitigation method of parallel-plate waveguide (PPW) noises excited from signal vias due to the mode conversion of desired propagation modes into parasitic PPW modes in multilayer printed circuit boards (PCBs) has been proposed. The mitigation of PPW noises has been achieved using virtual islands with shorting vias. The shorting vias are used to provide the return current path with low impedances and the virtual islands are used to block the propagation of the PPW noises through PCBs. The transmission and coupling responses of signal vias applied to the virtual islands with shorting vias are calculated using the finite-difference time-domain method to show effectiveness of the proposed mitigation method of PPW noises. The PPW noises propagating through PPWs are dramatically suppressed and the electrical performances of signal vias in multilayer PCBs are improved using the proposed method. The effectiveness of the proposed mitigation method of PPW noises is also verified by measurements of S-parameters of signal vias in simple test boards applied to the virtual islands with shorting vias. The effects of geometrical parameters of the virtual islands on performances of signal vias are also investigated. The performances of signal vias applied to the virtual islands with shorting vias can be improved up to higher frequency by reducing the size of virtual islands. The effect of the gapwidth of slots can be neglected. The effective number of shorting vias of the proposed mitigation method is four. Since several signal vias can be located at a virtual island, the needed number of shorting vias to obtain good transmission and coupling responses using the proposed mitigation method is less than half of that to obtain similar performance using only shorting vias.

Application of the non-uniform FDTD algorithm on an auto-adjustable mesh to the analysis of scattering parameters of a sandwiched-type coplanar waveguide with adjacent vias in PCBs

In this paper, we analyse scattering parameters for a sandwiched-type coplanar waveguide (SCPW) with three pairs of vias that are adjacent to each other. The above structure is frequently encountered in printed circuit board (PCB) designs, and is analysed by using a non-uniform finite difference time domain (FDTD) algorithm on an auto-adjustable mesh. The mesh generator developed for this algorithm can efficiently generate the files for the geometry—as well as for the material parameters—that serve as the inputs to the non-uniform FDTD solver. In addition, the generator has numerous graphical functions that not only ensure accuracy of generated data files but also make them convenient for the user. We carry out an extensive parametric study and show that the S -parameters are very dependent on the geometrical parameters of the vias, especially at high frequencies.