VHDL Statements Research Articles

DESIGN TIMED FSM WITH VHDL MOORE PATTERN

Context. The relevance of the work consists in the development of computer-aided design methods for automatic real-time logic control devices by developing a single template in a synthesized subset of the hardware description language in the style of automatabased programming with implementation on the PLD hardware platform (FPGA, CPLD). Development of the description template for timed control finite state machines (FSM) in the hardware description language VHDL, automated synthesis and implementation of the model in PLD (FPGAs, CPLDs) using Xilinx ISE, subsequent analysis of the received circuit implementation for compliance with values of timing parameters of the circuit after implementation.Objective. The aim of the work is to develop principles for constructing models of timed control FSM in the VHDL hardware description language. In this work, we solved the problem of constructing a pattern for describing models of timed control Moore FSM using VHDL, automated synthesis and implementation of the obtained VHDL model in PLDs (FPGA, CPLD) using Xilinx ISE and subsequent analysis of the resulting circuit implementation for compliance with values of timing parameters of the circuit after implementation.Method. Realization of models’ parameters of timed FSM in logical control systems using VHDL statements. Development of VHDL language constructions of timed FSM models for timing parameters implementation that provide the correct automated synthesis and implementation of these models in PLDs (FPGA, CPLD) using CAD tools Xilinx ISE.Results. Synthesis and implementation of proposed templates of VHDL-models of timed control Moore FSM in logic control systems by XILINX ISE CAD tools confirmed the receipt of not redundant circuits in PLD (FPGA, CPLD), and simulation after implementation showed the efficiency of such models.Conclusions. The work solves the problem of computer-aided design of timed control FSM in real-time logic control systems. To solve this problem, VHDL-models of timed control Moore FSM were developed, which made it possible to implement control FSM with time constraints, timeouts and output delays. Automated synthesis and simulation of VHDL models based on the developed templates confirmed the efficiency and correctness of the proposed models.The scientific novelty of the work consists in the further development of methods for constructing templates of HDL models of timed control Moore FSM, which made it possible to implement control FSM with time constraints, timeouts and output delays, as well as perform their correct automated synthesis and simulation.The practical value of results is in the development of procedures for constructing VHDL models of timed Moore control FSM in real-time logic control systems, which made it possible to automate the synthesis of control FSM taking into account the possibility of processing external events and implementing arbitrary delays for output signals and to increase the flexibility and speed of designed systems. The developed procedures can be useful for designers of timed control FSM in Xilinx ISE.

Debugging VHDL Designs: Introducing Multiple Models and First Empirical Results

Debugging is a time-consuming task. This holds especially for large programs that are usually written by different groups of programmers. An example for this observation is the hardware design domain. Nowadays hardware designs are written in special hardware description language, e.g., VHDL, by groups which work in different companies and places. Moreover, there is a high pressure for completing the system in time with a very high quality because of the huge costs for correcting a bug after manufacturing the circuit. In order to decrease time for debugging we introduce an approach for diagnosis of VHDL hardware designs and present first empirical results. In contrast to other debugging approaches we make use of model-based diagnosis which is a general diagnosis approach. The models we use are logical descriptions of the syntax and semantics of a VHDL program that can be automatically derived from the program at compile time. The main part of this paper describes a general model and the derivation of specialized models that capture only some aspects of the program. The specialized models should be used in a specific debugging situation where they deliver the most appropriate solution in reasonable time. In order to select such a model we propose the use of a probability-based selection strategy. For example, larger programs should be debugged using a model only distinguishing concurrent VHDL statements and not sequential statements. As a result of multi-model reasoning in this domain we expect performance gains allowing to debug larger designs in a reasonable time, and more expressive diagnosis results.

Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming

A method for generation of design verification tests from behavior-level VHDL programs is presented. The method generates stimuli to execute desired control-flow paths in the given VHDL program. This method is based on path enumeration, constraint generation and constraint solving techniques that have been traditionally used for software testing. Behavioral VHDL programs contain multiple communicating processes, signal assignment statements, and wait statements which are not found in traditional software programming languages. Our model of constraint generation is specifically developed for VHDL programs with such constructs. Control-flow paths for which design verification tests are desired are specified through certain annotations attached to the control statements in the VHDL programs. These annotations are used to enumerate the desired paths. Each enumerated path is translated into a set of mathematical constraints corresponding to the statements in the path. Methods for generating constraint variables corresponding to various types of carriers in VHDL and for mapping various VHDL statements into mathematical relationships among these constraint variables are developed. These methods treat spatial and temporal incarnations of VHDL carriers as unique constraint variables thereby preserving the semantics of the behavioral VHDL programs. Constraints are generated in the constraint programming language CLP(R) and are solved using the CLP(R) system. A solution to the set of constraints so generated yields a design verification test sequence which can be applied for executing the corresponding control path when the design is simulated. If no solution exists, then it implies that the corresponding path can never be executed. Experimental studies pertaining to the quality of path coverage and fault coverage of the verification tests are presented. >

OO-VHDL. Object-oriented extensions to VHDL

Object-oriented extensions to hardware description languages let engineers model systems at a higher level of abstraction, thus helping them manage design complexity and maximize component reuse. OO-VHDL, the object-oriented extension of VHDL that we describe in this article, supports the VHDL computation model and the reactive computation model within the same system. We hope this will help modelers develop a smooth transition from abstract models to detailed hardware models. In implementing the extensions, we were guided by one goal: providing the language to modelers as quickly as possible. This meant OO-VHDL had to be usable in current VHDL simulation environments. Thus, we have implemented a preprocessor that translates OO-VHDL to VHDL and a debugging tool that maps VHDL statements into the OO-VHDL statements from which they were derived.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>