VHDL Specification Research Articles

Hardware implementation of DIRLS mismatched compressor applied to a pulse-Doppler radar system

In this work, the hardware implementation of a digital mismatched pulse compressor and its application to a pulse-Doppler radar system are presented. The emphasis is to use one generalized compressor with reloading coefficient capability for several different types of signals. This implementation starts with a generic VHDL specification and then it is developed on FPGA architecture. The compression filter implementation on FPGA lets us eliminate special chips previously needed. The achieved design can be adapted to different computational requirements, easily modifying its data path and the length of the used signal sequence. From the experimental results it is known that this approach appears to work well for chirp and discrete phase matched/mismatched pulse compression and it outstands when TB is of order 1000. Also, it fits for arbitrary spread spectrum waveforms. The design performances have been analyzed modifying the used precision and the length of the used signal sequences.

An FPGA-based approach to the automatic generation of VHDL code for industrial control systems applications: A case study of MSOGIs implementation

When used for specifying control systems, system level design tools such as Xilinx System Generator (XSG) allows the use of Simulink for designs based on Field Programmable Gate Arrays (FPGAs). This increases productivity by reducing the wide gap between control system designers and FPGA-based implementations. However, there is still a need for new methods to bridge the gap since a direct implementation from XSG may not be an optimal solution when constraints are imposed. This is particularly true for resource-dominated circuits, where the number of operational units exceed the number of available resources. This paper presents both a methodology and a tool aimed at automatically reducing the required resources, in particular in systems where the required sampling period is greater than the computation time delay. An automatic process of converting XSG specifications into efficient Very High Speed Integrated Circuit Hardware Description Language (VHDL) code is described. The process mainly involves customized fixed-point hardware definition, Data Flow Graph (DFG) extraction, resource-constrained and latency-constrained scheduling and VHDL specification of the system, inter alia. This solution considerably improves on the results obtained by XSG.

Real-time implementation of an efficient correlator for complementary sets of four sequences applied to ultrasonic pulse compression systems

Complementary sequences are being employed to improve the results obtained in many sensorial systems where it is necessary to enhance the signal to noise ratio imposed by the environment. This improvement is achieved at the expense of increasing the computational complexity of the signal processing tasks. This work presents the hardware implementation of an efficient correlator for complementary sets of four sequences and its application to an ultrasonic pulse compression system. This implementation starts with a generic VHDL specification and then it is developed on an FPGA architecture. The achieved design can be adapted to different computational requirements, easily modifying its datapath and the length of the used sequences.

VHDL Specification Methodology from High-level Specification

Design complexity has been increasing exponentially this last decade. In order to cope with such an increase and to keep up designers' productivity, higher level specifications were required. Moreover new synthesis systems, starting with a high level specification, have been developed in order to automate and speed up processor design. This study presents a VHDL specification methodology aimed to extend structured design methodologies to the behavioral level. The goal is to develop VHDL modeling strategies in order to master the design and analysis of large and complex systems. Structured design methodologies are combined with a high-level synthesis system, a VHDL based behavioral synthesis tool, in order to allow hierarchical design and component re-use.

Identification of design errors through functional testing

Verification of the functionality of VHDL specifications is one of the primary and most time consuming tasks of design. However, it must necessarily be an incomplete task because it is impossible to completely exercise the specification by exhaustively applying all input patterns. We present a two-step strategy based on symbolic analysis of the VHDL specification, using a behavioral error model. First, we generate a reduced number of functional test vectors for each process of the specification by using a new analysis metric which we call bit coverage. The error model based on this metric allows the identification of possible design errors represented by redundancies in the VHDL code. Then, through the definition of a controllability measure, we verify if these functional test vectors can be applied to the process inputs when it is interconnected to other processes. If this is not the case, the analysis of the nonapplicable inputs provides identification of possible design errors due to erroneous interconnections. The bit-coverage provides complete statement, condition and branch coverage; and we experimentally show that it allows the identification of possible design errors. Identification and removal of design errors improves the global testability of a design.

Design of VHDL-based totally self-checking finite-state machine and data-path descriptions

This paper presents a complete methodology to design a totally self-checking (TSC) sequential system based on the generic architecture of finite-state machine and data path (FSMD), such as the one deriving from VHDL specifications. The control part of the system is designed to be self-checking by adopting a state assignment providing a constant Hamming distance between each pair of binary codes. The design of the data path is based on both classical methodologies (e.g., parity, Berger code) and ad hoc strategies (e.g., multiplexer cycle) suited for the specific circuit structure. Self-checking properties and costs are evaluated on a set of benchmark FSM's and on a number of VHDL circuits.

Hardware/software codesign for embedded signal processing

In this paper, we first propose a target board architecture suitable for rapid prototyping of various embedded applications. The target board is designed to be a PC plug-in card which contains a TI C30 DSP processor and up to four Xilinx XC5204 FPGAs for the hardware/software codesign. We next define the interface and communication protocols between the hardware and software sections. Finally, a HW/SW codesign environment which takes VHDL specification and partitions the design on the VHDL sub-program level is described. The partitioned designs will be augmented with the defined communication interface. High level synthesis and parallel DSP code generation are next employed to realize the realize the respective designs.

Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST

This paper proposes a new testability analysis and test-point insertion method at the register transfer level (RTL), assuming a full scan and a pseudorandom built-in self-test design environment. The method is based on analyzing the RTL synchronous specification in synthesizable very high speed integrated circuit hardware descriptive language (VHDL). A VHDL intermediate form representation is first obtained from the VHDL specification and then converted to a directed acyclic graph (DAG) that represents all data dependencies and flow of control in the VHDL specification. Testability measures (TMs) are computed on this graph. The considered TMs are controllability and observability for each bit of each signal/variable that is declared or may be implied in the VHDL specification. Internal signals of functional modules (FMs) such as adders and comparators are also analyzed to compute their controllability and observability values. The internal signals are obtained by decomposing at the RTL large FMs into smaller ones. The calculation of TMs is carried out at a functional level rather than the gate level, to reduce or eliminate errors introduced by ignoring reconvergent fanouts in the gate network, and to reduce the complexity of the DAG construction. Based on the controllability/observability values, test-point insertion is performed to improve the testability for each bit of each signal/variable. This insertion is carried out in the original VHDL specification and thus becomes a part of it unlike in other existing methods. This allows full application of RTL synthesis optimization on both the functional and the test logic concurrently within the designer constraints such as area and delay. A number of benchmark circuits were used to show the applicability and the effectiveness of our method in terms of the resulting testability, area, and delay.

Software methodologies in VHDL code analysis

At a high level of abstraction, the VHDL specification of the functionalities that a circuit can perform is given by defining the behavioral model. Similarity with procedural programming languages is suggested to tailor some software analysis techniques to VHDL behavioral description analysis. The aim is to retrieve information on the final circuit from its specifications. This paper presents several analyses of the code aimed at identifying significant properties of the final circuit from the synthesis and testability points of view.

Functional design for testability of control-dominated architectures

Control-dominated architectures are usually described in a hardware description language (HDL) by means of interacting FSMs. A VHDL or Verilog specification can be translated into an interacting FSM (IFSM) representation as described here. The IFSM model allows us to approach the testable synthesis problem at the level of each FSM. The functionality is modified by the addition of transparency to data flow. The complete testability of the IFSM implementation is thus achieved by connecting fully testable implementations of each modified FSM. In this way, test sequences separately generated for each FSM are directly applied to the IFSM to achieve complete fault coverage. The addition of test functionality to each FSM description, and its simultaneous synthesis with the FSM functionality, produces a lower area overhead than that necessary for the application of a partial-scan technique. Moreover, the test generation problem is highly simplified since it is reduced to the test generation for each separate FSM.

A VLSI Image Processing Architecture Dedicated to Real-Time Quality Control Analysis in an Industrial Plant

In this paper, we present a VLSI architecture for real-time image processing in quality control industrial applications: automation of the visual inspection phase of mechanical parts treated by the Fluorescent Magnetic Particle Inspection method for structural-defect detection. The VLSI architecture implements a highly constrained neural network tailored for this specific application: the multi-layer perceptron with strictly local connections. The learning of the weights is performed off line by using the adaptive simulated-annealing algorithm. The neural network has been trained on real plant data: recognition results of the training and classification tasks compare favorably with those obtained by expert human operators.The VLSI architecture receives as input the image (taken on-line on the plant) of a mechanical part and it will find out if at least one structural surface defect is present. The VLSI architecture was optimized, through a set of transformations on the high-level VHDL specifications of the neural network algorithm, to reach real-time operating conditions. Following the proposed approach and the designed architecture, we designed and successfully tested a custom VLSI chip for the real-time implementation of the recognition task.

Hardware/software codesign in the Estelle and VHDL environments

Modern industrial high-speed protocols and networks require the use of communication controllers that must handle severe real-time constraints. It will become increasingly difficult to implement them entirely in software, because their implementations would be too slow and offer unacceptable delays. Unfortunately, presently, a big gap exists between the software and hardware development environments which makes it hard to analyze the overall system specifications and performance. In this paper, we attempt to contribute to the integration between these two environments using two standard specification techniques: Estelle and VHDL, the former for distributed systems and the latter for hardware system components. We introduce the basis for a translation system from Estelle to VHDL specifications. We also illustrate the application of our translation rules to a protocol example.