VGA Interface Research Articles

Research on the Coupling Effect of Communication Display Interface under Strong Electromagnetic Pulse

In the high-altitude electromagnetic pulse (HEMP) environment, high-intensity broadband electromagnetic pulse energy is transmitted to the display interface circuit through the interconnection cable, causing interference or damage to the internal electronic components and chips, resulting in various damage effects such as the display cannot be displayed normally, and even restart. To investigate the coupling effect of strong electromagnetic pulses on the display interface circuit, the existing field-line coupling model is utilized as the basis of this study, with a specific focus on the VGA interface. The influence of different terminal impedances on the coupling effect is examined, aiming to determine the significance of terminal impedances in the simulation estimation of interface circuit coupling response. A HEMP coupling signal loop model is established based on the signal loop defined in the VGA datasheet, replicating the normal working conditions of VGA. HEMP pulse injection experiments are conducted to compare the response waveforms of the simulated VGA interface equivalent impedance circuit model with the measured data. This allows the accuracy of the established equivalent impedance model to be verified using key parameters.

Operation description and creating an analog VGA output on the debugging board when making programs for CNC machines

The priority task of the development of mechanical engineering is complex mechanization and automation of technological processes of mechanical processing. This problem can be solved by the introduction of machine tools and machine complexes with numerical control. CNC equipment combines the flexibility of universal and high performance of special automatic equipment, which significantly changes the nature of production and makes it mobile, meeting the requirements for continuous improvement and updating of mechanical engineering products. However, such equipment is quite complex, and its acquisition is associated with large financial costs, therefore, the problem of efficient use of CNC machines is a priority for most mechanical engineering enterprises and is inextricably linked with the need to create various programs. The article presents a theoretical analysis of the VGA interface, as well as a practical implementation of this interface, written in the Verilog programming language, on the Terasic DE10-Lite debugging board, with the MAX10 10M50DAF484C7G programmable logic integrated circuit and other peripheral modules. The practical significance of the work is familiarizing with programmable logic integrated circuits of the Intel FPGA family, obtaining basic knowledge in working with the Quartus Lite computer-aided design system (CAD), and learning the basics of programming programmable logic integrated circuits in the Verilog language. In the course of the work, the algorithm for writing code in the Verilog programming language for implementing the VGA interface on the DE10-Lite debugging board was described in detail. The software and mathematical excerpts used in the work are publicly available on the Internet, which allows anyone to carry out similar work and make sure that the written codes and the obtained conclusions are correct. This work can be used not only for writing programs for machine tools, but also for teaching students in the field of developing electronic devices in terms of their algorithmization and for organizing laboratory work, as well as for creating and designing real devices both in production and within a higher educational institution, for example, for developing laboratory work using specialized CAD. Familiarization and study of this programming language are conducted within the walls of one of the leading engineering universities of the Russian Federation, the Bauman Moscow State Technical University.

ISODATA SOPC-FPGA implementation of image segmentation using NIOS-II processor

<p>This paper presents an FPGA image segmentation-binarization system based on<em> </em>Iterative Self Organizing DATA <em>(ISODATA)</em> threshold using histogram analysis for embedded systems. The histogram module computes pixels levels statistics which are used by the ISODATA algorithm module to determine the segmentation threshold. In our case, this threshold binarizes a gray-scale image into two values 0 or 255. The prototype of the complete system uses an ALTERA CYCLONE-II DE2 kit with a lot of component and interfaces, such as the SD-CARD reader or a camera to read the image to be segmented, the FPGA which will implement the intellectual property (IP) core calculation with the NIOS processor, the VGA interface to view the results, and possibly of the ETHERNET interface for data transfer via internet. The use of FPGA contains the ISODATA, histogram, NIOS processor and others custom altera IPs hardware modules greatly improves processing speed and allows the binarization application to be embedded on a single chip. For the project elaboration, we have used QUARTUS-II software for the hardware development part with VHDL description, SOPC-builder or QSYS for the integration of NIOS-system, and NIOS-II-STB-ECLIPSE for the software program with eclipse c++ langage.</p><p> </p>

FPGA Implementation of Improved Security Approach for Medical Image Encryption and Decryption

Securing medical images is a great challenge to protect medical privacy. An image encryption model founded on a complex chaos-based Pseudorandom Number Generator (PRNG) and Modified Advanced Encryption Standard (MAES) is put forward in this paper. Our work consists of the following three main points. First, we propose the use of a complex PRNG based on two different chaotic systems which are the 2D Logistic map in a complex set and Henon’s system in the key generation procedure. Second, in the MAES 128 bits, the subbytes’ operation is performed using four different S-boxes for more complexity. Third, both shift-rows’ and mix-columns’ transformations are eliminated and replaced with a random permutation method which increases the complexity. More importantly, only four rounds of encryption are performed in a loop that reduces significantly the execution time. The overall system is implemented on the Altera Cyclone III board, which is completed with an SD card interface for medical image storage and a VGA interface for image display. The HPS software runs on μClinux and is used to control the FPGA encryption-decryption algorithm and image transmission. Experimental findings prove that the propounded map used has a keyspace sufficiently large and the proposed image encryption algorithm augments the entropy of the ciphered image compared to the AES standard and reduces the complexity time by 97%. The power consumption of the system is 136.87 mw and the throughput is 1.34 Gbit/s. The proposed technique is compared to recent image cryptosystems including hardware performances and different security analysis properties, such as randomness, sensitivity, and correlation of the encrypted images and results prove that our cryptographic algorithm is faster, more efficient, and can resist any kind of attacks.

An Improved Algorithm for Refinement of Overlapping Images of Marine Organisms

Li, K.; Jia, L., and Shi, X., 2020. An improved algorithm for refinement of overlapping images of marine organisms. In: Malvarez, G. and Navas, F. (eds.), Global Coastal Issues of 2020. Journal of Coastal Research, Special Issue No. 95, pp. 67–71. Coconut Creek (Florida), ISSN 0749-0208.Aiming at the shortcomings of the current ocean Ocean image edge detection algorithm, such as poor real-time performance, slow Ocean image processing and limited storage space, an improved ocean Ocean image overlay Ocean image refinement algorithm is designed. Collect overlapping Ocean images of marine organisms and store large amounts of Ocean images in SDRAM memory; use traditional SOBEL operators to detect overlapping portions of ocean Ocean images, use non-maximum suppression to refine Ocean image edges, and clearly and accurately display ocean edges through VGA interface Ocean image. The experimental results show that the method can locate the edge of the overlapping Ocean images of marine organisms more accurately, and the refinement process has better real-time performance, which can be applied to more complex edge detection of overlapping Ocean images of marine organisms.

Research on LCD-VGA Conversion Technology Based on ARM Microprocessor

LVDS-VGA conversion design for embedded system is proposed by using VGA interface timing as standard, ARM chip S59V210 as CPU, and D/A chip SDA7123 for signal conversion, On one hand, LCD controller of S5PV210 chip is configured to allow digital signals to be generated via LVDS interface. On the other hand, D/A chip SDA7123 converts digital signals into analog signals, enabling normal video displaying on VGA interface terminal. This solution has been proven to deliver good display results for video signals of varying resolution, like 800*600, 1024*768. It features low system impact, high efficiency and reliability, suitable to be widely adopted in embedded application.

Arquitectura FPGA para Simulación de Aprovisionamiento de Alimentos en Colonias de Hormigas Artificiales

Este artículo presenta algunos resultados en relación con el diseño y la implementación de una arquitectura que soporta una plataforma experimental para simular el proceso de alimentación de las colonias de hormigas. Los algoritmos Ant-system y Ant-Cycle modelan el comportamiento de las hormigas. La plataforma permite cambiar parámetros como la cantidad y la velocidad de las hormigas, la cantidad y ubicación de los alimentos y el radio y la frecuencia de difusión de la feromona de las hormigas. Estos parámetros se visualizan a través de una interfaz VGA. La implementación de hardware se lleva a cabo sobre tecnología FPGA de Xilinx©. La teoría detrás de este diseño considera que los comportamientos complejos pueden surgir de sistemas con una estructura simple . Este trabajo se enfrenta a la pregunta acerca de la complejidad global emergente de un sistema cuya complejidad estructural es mínima o inexistente.

Research of Visual Stimulation Method and Design of Visual Stimulator Based on Brain-Computer Interface

Brain Computer Interface (BCI) is a new ways of communicating with outside for the loss of some or all of the muscles controlling function of the patients. And the BCI is to set up a new information communication and control channel though the computer or other electronic device between the human brain and the external environment that does not depend on the peripheral nerve and muscle tissue. Firstly, this paper studies the methods of visual stimulation based on Brain Computer Interface that classified by stimulating form can be divided into flash simulation and figures simulation and classified by stimulating frequency can be divide into transient visual stimulation and steady-state visual stimulation. Then, using FPGA and the VGA interface designed of the visual stimulator that can be used to acquisition of steady-state visual evoked potential. Finally, adopting EEG signal processing platform verify this simulator. After numbers of verification, this simulator obtains a good desired result which achieved over 80% accuracy rate.

Application of AM-OLED Micro-Display in Stereo Display System

OLED micro-display is applied widely in the HMD stereo display field. Based on dual 0.5 inch 800×600 high resolution AM-OLED displays, we proposed a 3D circuit design scheme which used PCs VGA interface as video input, PIC18LF2550 as the MCU. According to the principle of the human eye binocular disparity, PC stereo video sources achieved odd frames and even frames displaying simultaneous in two AM-OLED panels, which implemented the 3D function. Display system has been tested by playing the stereoscopic video source of the left and right sides format form the PC and the effect presented a good performance which verified the effectiveness of the proposed scheme.

TFT LCD Driver Board Design Based on the AD9985A Chip and the EPM3128A Chip

On the basis of the introduction of the TFT color LCD principle and the analysis of the VGA interface standard, a TFT LCD driver board design program based on the AD9985A chip and the EPM3128A chip is proposed. A system block diagram of the TFT LCD driver board is designed. Then the main circuit design of the system is described in detail, including the power circuit design, the analog interface chip AD9985A circuit design and the programmable logic device EPM3128A circuit design. Finally, the main content of software design are introduced. Practice shows that the design is feasible and effective.