Very Large Scale Integration Process Research Articles

Energy-Efficient High-Throughput VLSI Architectures for Product-Like Codes

Implementing forward error correction (FEC) for modern long-haul fiber-optic communication systems is a challenge, since these high-throughput systems require FEC circuits that can combine high coding gains and energy-efficient operation. We present very large scale integration (VLSI) decoder architectures for product-like codes for systems with strict throughput and power dissipation requirements. To reduce energy dissipation, our architectures are designed to minimize data transfers in and out of memory blocks, and to use parallel noniterative component decoders. Using a mature 28-nm VLSI process technology node, we showcase different product and staircase decoder implementations that have the capacity to exceed 1-Tb/s information throughputs with energy efficiencies of around 2 pJ/b.

Spike Timing Dependent Plasticity (STDP) can Ameliorate Process Variations in Neuromorphic VLSI

A transient-detecting very large scale integration (VLSI) pixel is described, suitable for use in a visual-processing, depth-recovery algorithm based upon spike timing. A small array of pixels is coupled to an adaptive system, based upon spike timing dependent plasticity (STDP), that aims to reduce the effect of VLSI process variations on the algorithm's performance. Results from 0.35 microm CMOS temporal differentiating pixels and STDP circuits show that the system is capable of adapting to substantially reduce the effects of process variations without interrupting the algorithm's natural processes. The concept is generic to all spike timing driven processing algorithms in a VLSI.

The modeling, characterization, and design of monolithic inductors for silicon RF IC's

The results of a comprehensive investigation into the characteristics and optimization of inductors fabricated with the top-level metal of a submicron silicon VLSI process are presented. A computer program which extracts a physics-based model of microstrip components that is suitable for circuit (SPICE) simulation has been used to evaluate the effect of variations in metallization, layout geometry, and substrate parameters upon monolithic inductor performance. Three-dimensional (3-D) numerical simulations and experimental measurements of inductors were also used to benchmark the model accuracy. It is shown in this work that low inductor Q is primarily due to the restrictions imposed by the thin interconnect metallization available in most very large scale integration (VLSI) technologies, and that computer optimization of the inductor layout can be used to achieve a 50% improvement in component Q-factor over unoptimized designs.

A rule-based VLSI process flow validation system with macroscopic process simulation

As the integration scale of very large-scale integration (VLSI) circuits increases, it is becoming increasingly difficult to design long and complex process flows because there is a great amount of knowledge required in VLSI process technology. To assist in process-flow design, a rule-based validation system has been developed. This system checks designed process flows by using process knowledge related to contamination, cleaning methods, and the various constraints between the wafer structure and the process or equipment. It can point out error conditions that lead to such destructive results as contamination of the process equipment. The system applies process knowledge, expressed as if/then rules, to the process conditions and to macroscopic wafer structures derived from rule-based simulation. Due to the complexity of VLSI multilayered structures, information related to wafer structure is very important. This information can be obtained by rule-based simulation of such various macroscopic attributes of wafer structure as substance, contamination, and layer thickness. The validation system can precisely check various process flows and substantially improve the efficiency and quality of process-flow design. >

Future very-large-scale integration technology

Abstract Emerging technologies for very-large-scale integration (VLSI) process and device architecture are discussed. A new domain of submicron technology for 16 Mbits and beyond has recently been developed on the basis of unique surface chemistry on a cooled substrate in the temperature range from −20 to −130 °C. Reactive ion etching at low temperatures has dramatically improved the anisotropy, pattern shift and selectivity. Also, low temperature remote plasma chemical vapour deposition (CVD) has achieved complete planarization of device surfaces. Pattern projection of thin films has become possible by using excimer-laser-induced cryogenic CVD. All these findings have indicated the significant importance of controlling adsorbate-solid surface interactions in future VLSI process technology. As for device architecture a new type of silicon chip such as a three-dimensional optically coupled common memory will be developed in addition to the conventional high density VLSI memories.