Very Large Scale Integrated Circuits Research Articles

FATE: A Flexible FPGA-Based Automatic Test Equipment for Digital ICs

The limits of chip technology are constantly being pushed with the continuous development of integrated circuit manufacturing processes and equipment. Currently, chips contain several billion, and even tens of billions, of transistors, making chip testing increasingly challenging. The verification of very large-scale integrated circuits (VLSI) requires testing on specialized automatic test equipment (ATE), but their cost and size significantly limit their applicability. The current FPGA-based ATE is limited in its scalability and support for few test channels and short test vector lengths. As a result, it is only suitable for testing specific chips in small-scale circuits and cannot be used to test VLSI. This paper proposes a low-cost hardware and software solution for testing digital integrated circuits based on design for testability (DFT) on chips, which enables the functional and performance test of the chip. The solution proposed can effectively use the resources within the FPGA to provide additional test channels. Furthermore, the round-robin data transmission mode can also support test vectors of any length and it can satisfy different types of chip test projects through the dynamic configuration of each test channel. The experiment successfully tested a digital signal processor (DSP) chip with 72 scan test pins (theoretically supporting 160 test pins). Compared to our previous work, the work in this paper increases the number of test channels by four times while reducing resource utilization per channel by 37.5%, demonstrating good scalability and versatility.

Design and analysis of 4-bit absolute-value comparator in 65nm technology using hybrid TG/CMOS

Comparators are an important part of the calculator architecture, and rapid advances in semiconductor and electronics technology have placed higher demands on their performance. Optimization of digital systems involves several levels in order to make improvements in their power consumption, delay, and other parameters. This paper designs a low-power, high speed, and area efficient 4-bit absolute-value comparator, which utilizes a static Complementary Metal-Oxide-Semiconductor (CMOS) and Transmission Gate (TG) hybrid structure. The design optimizes the system at the level of separate circuit blocks, logic gates and transistors. The logic functions are realized by means of transcoding and magnitude Comparison, and the input signals are all driven by two-stage inverters. MUX and XOR with excellent performance of TG structure are implemented using simulation and analysis. In this paper, the transistor sizes and supply voltages of each logic gate are calculated and optimized using MATLAB by applying logic effort theory. The design uses a 65nm technology, and transient simulation of the overall system in Cadence successfully realizes its logic functions with 0.83ns delay and 49.6uw power consumption, proving the effectiveness of the design. This study based on theoretical calculations and simulations is a good reference for the design and theoretical study of very large-scale integrated circuits (VLSI).

Estimating R, L and C in Arithmetic Circuits using ML

In Very Large Scale Integration (VLSI) circuits, the estimation techniques for resistors (R), inductors (L), and capacitors (C) heavily rely on segmented circuit analysis, which involves usage of complex mathematical simplification models. These methods have been conventionally applied to estimate the behavior of circuits, but when faced with systems featuring unique circuit architectures, they often encounter inaccuracies and limitations. The significance of adders as fundamental building blocks in intricate circuit design cannot be overstated. In such complex circuits, various parameters, including parasitic resistances, inductances, and capacitances, engage an indispensable effort in the analysis of delays and performance. However, the conventional estimation methods fail to address the complexities of these systems and the impacts of parasitics accurately. To overcome these challenges, this paper proposes a novel approach that harnesses the potential of machine learning algorithms. By integrating machine learning into the estimation process, the research aims to achieve specific and precise analysis methods that can cater to the needs of modern VLSI circuits. The proposed methodology involves collecting a comprehensive dataset using different adder circuits. From each individual adder circuit layout, the relevant information on resistors, capacitors, and inductors is carefully extracted and compiled. This dataset serves as the foundation for training the machine learning models. Three standard machine learning models are employed in this study: adaboost, Tree, and k-Nearest Neighbors (kNN). Their task is to predict the values of resistors, inductors, and capacitors based on the input data from the adder circuits. Among these models, adaboost proves to be the most effective, exhibiting superior performance by achieving a reduced root mean square error of about 0.008. When compared to the Tree and kNN models, adaboost stands out as the optimal choice for accurately estimating the R values in VLSI circuits.

Multi-Objective Genetic Algorithm-Based Technique for Achieving Low-Power VLSI Circuit Partition

Minimizing the power consumption of electronic systems is one of the most critical concerns in the design of integrated circuits for very large-scale integration (VLSI). Despite the reality that VLSI design is known for its compact size, low power, low price, excellent dependability, and high functionality, the design stage remains difficult to improve in terms of time and power. Several optimization algorithms have been designed to tackle the present issues in VLSI design. This study discusses a bi-objective optimization technique for circuit partitioning based on a genetic algorithm. The motivation for the proposed research is derived from the basic concept that, if some portions of a circuit's system are deactivated during the processor's idle time, the circuit's power consumption is automatically reduced. To reduce the overall system's power consumption, maximization of sleep time and minimization of net cuts are required. To achieve these, an effective fitness function has been constructed in such a way that the balance criteria are also maintained. The approach has been tested on a set of net lists from the ISPD'98 benchmark suite, each containing 10 to 30 nodes. The experimental results are compared with two existing methods that clearly indicate the acceptability of the suggested method. The suggested strategy achieves an average reduction of 24.69% and 31.46% for net cut, whereas average extensions of 15.20% and 12.31% are observed in sleep time when compared with two existing methods. The proposed method also achieves an average power efficiency of 14.98% and 12.09% with respect to these two state-of-the-art methods.

An efficient 3D IC partitioning approach using satin bowerbird optimization for reduced TSV count and improved heat dissipation

Net list partitioning achieves paramount importance in the physical architecture design step of Three Dimensional (3D) Very Large Scale Integrated (VLSI) circuits. The performance of all subsequent steps like floor layout, placement, pin assignment, and routing in the physical architecture design of the VLSI circuit are heavily affected by the outcomes of partitioning steps. Wire length between gates is reduced by 3D Integrated Circuit (IC) due to compact footprint as well as vertical inter connections among dies. This reduced wire length in turns responsible for less energy consumption and reduced connection delays. In this paper, Satin Bowerbird Optimization (SBO) is applied to solve 3D IC partitioning challenges. The suggested 3D IC partitioning technique is aimed at reducing the number of Through Silicon Vias (TSV) and measurements have also been taken to reduce heat dissipation. The presence of a significant amount of TSVs expands the chip area. 3D ICs have considerably greater densities of power because of advances in the technology and a vastly increased variety of components with high frequency. The heat generated by the used power has an impact on the performance and dependability of the chip. In this experiment, SBO is used as a multi-objective optimization method to achieve two objectives simultaneously - TSV count minimization and heat dissipation reduction. The performance of the suggested SBO - based approach is assessed utilizing the Giga Scale Research Center (GSRC) benchmark circuits. The applicability of the suggested technique is judged by comparing the outcomes with thermal-aware multilevel hyper-graph partitioning method. The findings of the comparison reveal that the suggested technique outperforms the thermal-aware multilevel hyper-graph partitioning approach by lowering the number of TSV count, maximum area requirement, and power density by 16.99%, 9.94% and 29.10% respectively. The performance of the experiment is also compared with existing Simulated Annealing and Tabu search based techniques. In both cases, the proposed method achieves better result by lowering TSV by 26.03% and 27.31%, and reducing area by 6.59% and 6.59%, respectively.

(Invited) Industrial Face of Nanotechnology

Ever since the proposal and demonstration of quantum dots in 1980 by Drs. A. Efros, Al. Efros and A. Ekimov, the relentless progress of nanotechnology has been unstoppable. And nowhere this progress is more evident than in the Si Very Large Scale Integrated Circuits (VLSI) and Thin Film Transistor (TFT) technologies. The minimum feature size of the Si VLSI with up to 2.6 trillion transistors on a chip was reduced to 3 nm in 2022 with plans for the 2 nm technology. TFTs fabricated on glass or even on cloth or paper enable integrated circuits with 50 nm tolerances over square meter sizes. These technologies have become disruptive with applications ranging from 5G and Beyond 5G communications to robotics, driverless cars, and electronic warfare. This talk will focus on the new counter-intuitive physics of ballistic transport required to support the design, characterization, and parameter extraction for nanoscale Si VLSI and TFT integrated circuits. Figure 1

(Invited) High-Performance Field-Effect Transistors Based on Two-Dimensional Materials for VLSI Circuits

Introduction Nowadays, the scaling of silicon very large-scale integration(VLSI) technologies has reached channel thicknesses of 7nm. However, further downscaling becomes increasingly difficult as the gate electrostatics require a substantial reduction of the channel thickness to about a fourth of the gate length. As a result, the actual gate length of high-performance(HP) FETs at the current state-of-the-art amounts to 16nm and is projected to stall at 12nm for the 1.5nm node and the following nodes, according to the International Roadmap for Devices and Systems(IRDS)[1]. For these nodes, two-dimensional(2D) materials could have the potential to replace silicon as the channel material. They can maintain sizable mobilities at atomic thicknesses, thus providing enhanced gate control in stacked channel nanosheet transistor structures[2]. Even though FETs based on 2D materials hold the promise to serve as FETs at the front end of the line, numerous challenges still need to be overcome. Downscaling Dimensions For ultra-scaled device designs, 2D materials can be used as a channel in stacked nanosheet FETs. In such a structure, the 2D material is gated from both sides, as depicted in Fig.1(a). By stacking multiple double-gated channels on top of each other, the required on-current density of around 1mA/μm can be achieved[3]. The first experimental demonstrations have achieved sub-5nm gate lengths[4] or, in a different design, a gate pitch of only 42nm[5], meeting the requirements for the 1.5nm node. While these prototypes show that 2D FETs can be scaled down, they have been fabricated in a laboratory. Many challenges must be overcome before such small devices can be fabricated in industry-compatible batch processes which require a high yield and low variability. Contact Engineering In order to enable sufficiently high on-current densities, small contact resistances to 2D semiconductors are required, which are inhibited by the formation of Schottky barriers at the metal to semiconductor interface. Schottky contacts to 2D materials are so prevalent because there is, on one side, a lack of stable doping schemes, and on the other side, pronounced Fermi-level pinning at the metal-to-semiconductor interface. Semi-metallic bismuth contacts can provide low-resistive contacts to n-type MoS2 FETs, as the bismuth suppresses the metal-induced gap states which pin the Fermi-level[6]. This way, a small contact resistance of 123Ωμm has been achieved, reaching the IRDS limit for the 1.5nm node. While comparable results have been realized for antimony contacts to n-type FETs, low-resistive contacts to p-type FETs are more challenging. Gate Stack Design A good gate stack for 2D FETs must provide excellent gate control while maintaining small gate leakage currents, which requires a capacitive equivalent thickness(CET) smaller than 0.9 nm. At these small CETs, a small gate leakage can only be obtained with a high-dielectric constant gate insulator and sizable band offsets, rendering some insulators, e.g. hexagonal boron nitride, unsuitable. Simultaneously, the gate insulator should form a van-der Waals interface with the 2D semiconductor, as otherwise, interface traps degrade the carrier mobility and the sub-threshold slope[7]. Charge traps within the insulator are the root cause of the limited stability and reliability of 2D FETs, as seen by a large hysteresis in the transfer characteristics or in pronounced Bias Temperature Instabilities(BTI). The electrical stability can be improved, if the defect bands in the gate insulator are energetically far away from the semiconductor’s conduction and valence band edges, see Fig.1(b)[8]. Conclusions Despite all the progress achieved within the last decade, the challenges for VLSI integration of 2D materials are enormous. First, stacked 2D FETs with scaled dimensions still need to be realized at an industrial scale. Second, despite low contact resistance demonstrations for n-type FETs, the resistances for p-type FETs are one order of magnitude too high. Finally, one of the most serious obstacles is identifying a suitable gate stack. Even though promising combinations of insulators to semiconductors have been suggested, like Bi2O5Se/Bi2O2Se, CaF2/MoS2 or SrTiO3/MoS2, it is at the moment unclear, which of them provides the best performance. Acknowledgments The authors thank for funding from the European Research Council under grant agreement no. 101055379.

Consumer Electronics Product Manufacturing Time Reduction and Optimization Using AI-Based PCB and VLSI Circuit Designing

Circuit design plays an essential role in all consumer electronics products. Printed circuit board (PCB) and very-largescale integration (VLSI) circuit designing requires optimization of the electronic components placement and wire routing to connect the components. Currently, circuit routing processes have been performed manually by experts, which greatly increases the cost of human resources and time. Such heuristic circuit designs are not optimized and may have errors, which is why automated circuit routing algorithms are important. However, it is difficult to obtain an optimal solution in circuit routing as it is an NPhard problem. In addition, poor circuit routing increases the wire length of the circuit, which causes an increase in circuit cost and weight as well as performance degradation. In order to achieve routing optimization, many technologies have been proposed, in which some have applied artificial intelligence (AI) to improve the overall performance and reduce the designing time. Accordingly, in this paper, routing problems in PCB and VLSI are explained, and proposed technologies to solve these routing problems are introduced. Especially, a detailed investigation and analysis of AI technologies grafted into circuit routing algorithms are explained, and the considerations for AI-based routing algorithms are presented.

An Efficient On-Chip Data Storage and Exchange Engine for Spaceborne SAR System

Advancements in remote sensing technology and very-large-scale integrated circuit (VLSI) have significantly augmented the real-time processing capabilities of spaceborne synthetic aperture radar (SAR), thereby enhancing terrestrial observational capacities. However, the inefficiency of voluminous data storage and transfer inherent in conventional methods has emerged as a technical hindrance, curtailing real-time processing within SAR imaging systems. To address the constraints of a limited storage bandwidth and inefficient data transfer, this study introduces a three-dimensional cross-mapping approach premised on the equal subdivision of sub-matrices utilizing dual-channel DDR3. This method considerably augments storage access bandwidth and achieves equilibrium in two-dimensional data access. Concurrently, an on-chip data transfer approach predicated on a superscalar pipeline buffer is proposed, mitigating pipeline resource wastage, augmenting spatial parallelism, and enhancing data transfer efficiency. Building upon these concepts, a hardware architecture is designed for the efficient storage and transfer of SAR imaging system data, based on the superscalar pipeline. Ultimately, a data storage and transfer engine featuring register addressing access, configurable granularity, and state monitoring functionalities is realized. A comprehensive imaging processing experiment is conducted via a “CPU + FPGA” heterogeneous SAR imaging system. The empirical results reveal that the storage access bandwidth of the proposed superscalar pipeline-based SAR imaging system’s data efficient storage and transfer engine can attain up to 16.6 GB/s in the range direction and 20.0 GB/s in the azimuth direction. These findings underscore that the storage exchange engine boasts superior storage access bandwidth and heightened data storage transfer efficiency. This considerable enhancement in the processing performance of the entire “CPU + FPGA” heterogeneous SAR imaging system renders it suitable for application within spaceborne SAR real-time processing systems.

Verification methods for complex-functional blocks in CAD for chips deep submicron design standards

The article discusses the design stages of very large-scale integrated circuits (VLSI) and the features of the procedure for verifying complex-functional VLSI blocks. The main approaches to microcircuit verification procedures are analyzed to minimize the duration of verification cycles. In practice, a combination of several approaches to verification is usually used.

Intelligent Systems and Photovoltaic Cells Empowered Topologically by Sudoku Networks

A graph invariant is a number that can be easily and uniquely calculated through a graph. Recently, part of mathematical graph invariants has been portrayed and utilized for relationship examination. Nevertheless, no reliable appraisal has been embraced to pick, how much these invariants are associated with a network graph in interconnection networks of various fields of computer science, physics, and chemistry. In this paper, the study talks about sudoku networks will be networks of fractal nature having some applications in computer science like sudoku puzzle game, intelligent systems, Local area network (LAN) development and parallel processors interconnections, music composition creation, physics like power generation interconnections, Photovoltaic (PV) cells and chemistry, synthesis of chemical compounds. These networks are generally utilized in disorder, fractals, recursive groupings, and complex frameworks. Our outcomes are the normal speculations of currently accessible outcomes for specific classes of such kinds of networks of two unmistakable sorts with two invariants K-banhatti sombor (KBSO) invariants, Irregularity sombor (ISO) index, Contraharmonic-quadratic invariants (CQIs) and dharwad invariants with their reduced forms. The study solved the Sudoku network used in mentioned systems to improve the performance and find irregularities present in them. The calculated outcomes can be utilized for the modeling, scalability, introduction of new architectures of sudoku puzzle games, intelligent systems, PV cells, interconnection networks, chemical compounds, and extremely huge scope in very large-scale integrated circuits (VLSI) of processors.

A Review on low-Power VLSI CMOS and CNTFET Circuits

Nowadays, power consumption is one of the primary considerations in the design of VLSI (Very Large Scale Integration) circuits based on complementary metal oxide semiconductors (CMOS) and carbon nanotube field effect transistors (CNTFET). This is because of the present circumstance. The fundamental reason for this is that power utilisation has been raised to the status of a top priority due to the improvements in integration and scaling as well as the constant increases in operating frequency. Additional power consumption from circuits and designs makes them challenging to implement in portable devices. The quantity of power lost during operation has an immediate effect on the cost of packaging the IC and systems. A variety of power dissipation sources and low power VLSI design strategies for CMOS and CNTFET-based circuits are discussed in this article.

Research Progresses on Suppressing the Short-Channel Effects of Field-Effect Transistor

Recently, with the continuous miniaturization and integration of microelectronic devices in all fields, the conventional MOSFET structure has suffered from severe short channel effects with continuous downsizing. In order to further improve the electrical properties of Very Large-Scale Integration Circuit (VLSI) and obtain the larger device integration density in circuits, new revolution in MOSFET technology is needed, which involves the innovations of new materials, new technologies, and new device structures. This paper explores device structure innovations in traditional planar transistors, such as the device performance enhancement via the high-κ/metal gate and especially the three-dimensional device structure—FinFET, as well as the subsequent development of gate-all-around FET proved to outperform FinFET. The development of high-performance devices based on new materials has become an imperative direction to break through the current bottleneck of silicon-based technologies. This paper focuses on an overview of transition-mental dichalcogenides and ferroelectric materials, including frontier research and current inadequacies. Based on these new approaches, VLSI manufacturing technology has seen many breakthroughs in recent years, which will successfully extend Moore's Law and further promote the development of emerging technologies in multiple fields.

A Space–Time Neural Network for Analysis of Stress Evolution Under DC Current Stressing

The electromigration (EM)-induced reliability issues in very large-scale integration (VLSI) circuits have attracted increased attention due to the continuous technology scaling. Traditional EM models often lead to overly pessimistic predictions incompatible with the shrinking design margin in future technology nodes. Motivated by the latest success of neural networks in solving differential equations in physical problems, we propose a novel mesh-free model to compute EM-induced stress evolution in VLSI circuits. The model utilizes a specifically crafted space–time physics-informed neural network (STPINN) as the solver for EM analysis. By coupling the physics-based EM analysis with dynamic temperature incorporating Joule heating and via effect, we can observe stress evolution along multisegment interconnect trees under constant, time-dependent, and space–time-dependent temperature during the void nucleation phase. The proposed STPINN method obviates the time discretization and meshing required in conventional numerical stress evolution analysis and offers significant computational savings. Numerical comparison with competing schemes demonstrates a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$52\times $ </tex-math></inline-formula> speedup with a satisfactory accuracy.

Diode Connected Transistor-Based Low PDP Adiabatic Full Adder in 7 nm FINFET Technology for MIMO Applications

Full adders are a core component and play an essential role in the design of contemporary very-large-scale integration (VLSI) integrated circuits. Low-power, high-speed adder design has been the subject of numerous different sorts of research. The never-ending process is still in progress. The saturation point for MOS-based VLSI circuit design has been reached. As a consequence, many additional issues arise when MOS devices are scaled down to the nanoscale range, including an increase in leakage power and a vulnerability to PVT variation. Hence, MOSFET alternatives have been looked after by VLSI industries. Future nanoscale VLSI circuits would benefit greatly from the use of FINFETs in place of MOS transistors. In this paper, two diode-connected transistors-based low power, high speed, and low-power–delay product (PDP) adiabatic logic full adders are proposed using 7 nm technology. DCT TSAA-I, DCT TSAA-II, DCT TCAA-I, and DCT TCAA-II are the names of the proposed structures. Power, speed, and power–delay product (PDP) performance of the proposed adders are compared with those of traditional full adders. According to the simulation outcomes, the proposed adder architectures offer the least PDP in comparison to the adders taken into consideration. On power and delay, the impact of changing variables like temperature, supply voltage, load capacitance, and frequency is seen. A 7 nm FINFET model has been used in the simulations, which were conducted using the Hspice simulation tool.

An Online Course Content for Undergraduate Students on Full-Custom Design of a Digital VLSI Circuit Using Open-Source Software

The Very Large-Scale Integration (VLSI) circuit design is a promising field for undergraduate students hoping to explore job opportunities in electronics circuit design companies. Therefore, several institutes in India offer VLSI courses to electronics engineering undergraduate students. In recent times, because of the pandemic, online classes appeared as an effective method of teaching; this helped in running of academic schedule smoothly without hampering the students’ learning process. In this paper online teaching content is presented to help the student learn digital VLSI circuit design using an open-source tool. This course content is particularly helpful in understanding the theoretical and practical design of a Complementary Metal Oxide Semiconductor (CMOS)-based logic function, with minimal effort by the faculty without access to campus software. The content starts with a digital logic function and its switch-level representation into PULL-UP and PULL-DOWN networks. Then the switch-level circuit with the help of Euler’s graph is translated into a stick diagram and then converted into a layout cell using the lambda design rule. An interesting approach to choosing the gate sequence in the stick diagram from Euler’s graph, and the simulation result of the layout cell are presented and discussed. The approach helped the students in understanding full custom CMOS logic function design, test, and validation, with less effort and time. The survey shows that 86% of the students were satisfied with the content and that the course content helped to achieve an 81% average pass percentage in the two online semesters.

Specially-Designed Out-of-Order Processor Architecture for Microcontrollers

In very large-scale integration circuit (VLSI) systems, microcontrollers are often implanted to manage the whole system to complete the given computing tasks. They play an essential part as regulators, which should allocate resources steadily and issue instructions promptly to drive functional units. However, most of the recent research focuses on the operation at the software level or the scheduling at the SoC level, ignoring the impact of the microarchitecture and the features of controlled sub-modules. This paper analyzes the requirements of microcontrollers in the VLSI system with various constraints and conditions that should be considered in the hardware implementation of such microarchitecture. Furthermore, this paper takes an open-source design using RISC-V ISA as the prototype to implement hardware microarchitecture. This design integrates the techniques of out-of-order processing, which are usually used on superscalar processors. As a result, the design quadruples the number of pipelined instructions, greatly alleviating the stalling of the instruction stream with a maximum extra look up table utilization of 18.37% in FPGA implementation.

Recurrent deep neural learning classification algorithm based high level synthesis in VLSI circuit with runtime adaptability

Electronics industry has attained huge development in last few decades due to the rapid increase in system design applications. With the growth of very large scale integration (VLSI) design, integrated circuits (ICs) are employed in many applications. VLSI design comprises many steps like system-level design, high-level synthesis (HLS), logic design, test generation, and physical design. HLS interprets behavior description and create digital hardware that executes the behavior. But, the power-process-voltage-temperature (PPVT) variation can causee many issues and reduce the performance of VLSI design circuits. In order to address these problems, Recurrent Deep Neural Learning Classification based High Level Synthesis (RDNLC-HLS) Model is designed for better runtime adaptability with minimal time consumption. VLSI circuits are designed with the behavioral input and the output performance is measured at runtime. The behavioral description of the circuit is taken as input. Then, source code compilation process translates high level specification into Intermediate Representation (IR) and converts to control/data flow graph (CDFG). CDFG reveals data and control dependencies between operations. The proposed Recurrent Deep Neural Learning Classification based High Level Synthesis (RDNLC-HLS) Model is designed for providing better runtime adaptability with minimal time consumption. Finally, Register Transfer Level Generation is carried out to yield better runtime adaptability with minimal time. Simulation results on ISCAS’89 Benchmark Dataset, shows that the RDNLC-HLS model increases the FUSA with minimal error rate and CAT.

A Review on Low Power VLSI Design Models in Various Circuits

Low power design is one of the primary goals for any integrated circuits. Very Large-Scale Integration (VLSI) is a kind of Integrated Circuit (IC) that consists of hundreds and hundreds of transistor connection into a small chip. The communication and computer applications have grown very faster in the past decade due to the development of VLSI circuit design as microcontroller and microprocessors. However, still the research on VLSI are moving faster towards the scope of power and area minimization. The paper gives an overview about the recent methodologies that have been developed for the performance improvement of VLSI design and it shows the future directions of the areas that are to be concentrated on VLSI circuit design.

Silicon Modeling of Spiking Neurons With Diverse Dynamic Behaviors

Since spiking neural networks (SNNs) can effectively simulate the information processing mechanism of the biological cortex, they are expected to bridge the gap between neuroscience and machine learning. The hardware simulation of large-scale SNNs requires a simple and versatile silicon neuron model framework. In this article, a spiking neuron circuit as the core device of SNNs is presented. The proposed neuron circuit can mimic the dynamics of different types of biological neurons by adjusting the bias voltage. In order to facilitate the implementation of the spiking neuron circuit based on complementary metal-oxide-semiconductor (CMOS) and reduce the overhead of the circuit area, a modified Mihalas–Niebur (MN) mathematical model is adopted. The improved MN model is biologically plausible and can still successfully display all dynamic behaviors observed in biology. The function of the proposed neuron circuit has been verified by the phase diagram analysis method. The simulation results show the designed neuron circuit can successfully replicate 15 of the 20 firing patterns exhibited by the biological cortex, which proves that the neuron can act as a universal spiking neuron in very large-scale integrated circuit (VLSI) neuromorphic networks.