VHSIC Hardware Description Language Research Articles

Generic FPGA Pre-Processing Image Library for Industrial Vision Systems.

Currently, there is a demand for an increase in the diversity and quality of new products reaching the consumer market. This fact imposes new challenges for different industrial sectors, including processes that integrate machine vision. Hardware acceleration and improvements in processing efficiency are becoming crucial for vision-based algorithms to follow the complexity growth of future industrial systems. This article presents a generic library of pre-processing filters for execution in field-programmable gate arrays (FPGAs) to reduce the overall image processing time in vision systems. An experimental setup based on the Zybo Z7 Pcam 5C Demo project was developed and used to validate the filters described in VHDL (VHSIC hardware description language). Finally, a comparison of the execution times using GPU and CPU platforms was performed as well as an evaluation of the integration of the current work in an industrial application. The results showed a decrease in the pre-processing time from milliseconds to nanoseconds when using FPGAs.

Design and Simulation of Clock Divider using VHDL

This paper presents the diesign and simulation of clock divider circuit using VHDL(VHSIC Hardware Description Language) on an FPGA(Field Programmable Gate Array). The clock divider circuit is a fundamental component in digital system for generating lower frequency clocks from a higher frequency reference clock. The paper starts up with simple divider where the clock is divided by even numbers, odd numbers and then later expands it into non- integer dividers. Keywords:- clock divider, D flipflop, FPGA

A Reconfigurable Hardware Realization for Real-Time Simulation of Cardiac Excitation and Conduction

Dynamic simulation of complex cardiac excitation and conduction requires high computational time. Thus, the hardware techniques that can run in real-time simulation were introduced. However, according to existing studies, the hardware simulation requires high power consumption and involves a large size of the physical parts. Due to the drawbacks, this research presents the adaptation of nonlinear Ordinary Differential Equation (ODE)-based cardiac excitable models of Luo-Rudy Phase I (LR-I) and FitzHugh-Nagumo (FHN) in a reconfigurable hardware of field-programmable gate array (FPGA). FPGA rapid prototyping using MATLAB Hardware Description Language (HDL) Coder was used to convert a fixed-point MATLAB Simulink blocks design of the cardiac models into a synthesizable VHSIC Hardware Description Language (VHDL) code and verified using the FPGA-In-the Loop (FIL) Co-simulator. The Xilinx FPGA Virtex-6 XC6VLX240T ML605 evaluation board was chosen as the FPGA platform. The cardiac excitation response characteristics using the LR-I model and the simulations of reentrant initiation and annihilation using the FHN model were verified in Virtex-6 FPGA. This means a new real-time simulation-based analysis technique of cardiac electrical excitation and conduction wassuccessfully developed using the reconfigurable hardware.

High-Capacity Data Processing with FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier

Encryption algorithms work with very large key values to provide higher security. In order to process high-capacity data in real-time, we need advanced hardware structures. Today, when compared to the previous designing methods, the required hardware solutions can be designed more easily by using Field Programmable Gate Array (FPGA). Over the past decade, FPGA speeds, capacities, and design tools have been improved. Thus, the hardware that can process data with high capacity can be designed and produced with lower costs. 
 The purpose of this study is to create the components of a high-speed arithmetic unit that can process high-capacity data, which can also be used for FPGA encoding algorithms.
 In this study, multiplication algorithms were analyzed and high-capacity adders that constitute high-speed multiplier and look-up tables were designed by using Very High-Speed Integrated Circuit Hardware Description Language (VHDL). The designed circuit/multiplier was synthesized with ISE Design Suite 14.7 software. The simulation results were obtained through ModelSIM and ISIM programs.

Design and Testing of a Wireless Communication Enabled FPGA Development Board: A Comprehensive Education and Application Platform from IoT to Circuit Design

Field Programmable Gate Array (FPGA) is an integrated circuit (IC) that can be reprogrammed or configured by the customer or designer after production for rapid prototyping and post-process development. In this study, a cost-effective FPGA development board is designed to create basic engineering education applications and implement them in real-time. The FPGA development board utilizes an Altera Cyclone IV E-series chip and includes Bluetooth and Wi-Fi modules to provide a wider range of applications. This integration simplifies the use of wireless communication in various projects and applications for researchers and engineers. To verify the accuracy of the proposed board, simulations of selected digital designs and Bluetooth applications were first performed in VHDL (Very High Speed Integrated Circuit Hardware Description Language) using Intel® Quartus® Prime Lite Edition software. Then, experiments were performed on the board following the pin assignment configurations. It was observed that the developed applications worked successfully on the FPGA development board. As a result, this board, equipped with Bluetooth and Wi-Fi modules, offers a fast and cost-effective solution for users in various fields such as mobile, robotics, smart home systems, and remote monitoring and control devices

Design of electronic clock and stopwatch based on FPGA and VHDL language

This paper designs a simple system that can include electronic clock and stopwatch based on FPGA(Field Programmable Gate Array) and VHDL(Very-High-Speed Integrated Circuit Hardware Description Language). The first chapter briefly introduces the research background. The second chapter introduces the theoretical basis of digital circuits and the hardware and software platform used in this paper. In the third chapter, the design of each sub-module of the system and the overall design of the system are carried out. This chapter is the core chapter of this article, which describes the functions of the module and explains the input and output ports. In this chapter, a core point of digital circuit design is reflected: combining modules that realize simple functions into modules that can realize complex functions. And integrate sub-modules that realize similar functions into a top-level module. The fourth chapter is the logic synthesis of the circuit. The fourth chapter shows the simulation of the core module function and the simulation of the system output. The conclusion section summarizes the interesting parts of the design of this paper.

Efficient Two-Stage Max-Pooling Engines for an FPGA-Based Convolutional Neural Network

This paper proposes two max-pooling engines, named the RTB-MAXP engine and the CMB-MAXP engine, with a scalable window size parameter for FPGA-based convolutional neural network (CNN) implementation. The max-pooling operation for the CNN can be decomposed into two stages, i.e., a horizontal axis max-pooling operation and a vertical axis max-pooling operation. These two one-dimensional max-pooling operations are performed by tracking the rank of the values within the window in the RTB-MAXP engine and cascading the maximum operations of the values in the CMB-MAXP engine. Both the RTB-MAXP engine and the CMB-MAXP engine were implemented using VHSIC hardware description language (VHDL) and verified by simulations. The implementation results demonstrate that the 16 CMB-MAXP engines achieved a remarkable throughput of about 9 GBPS (gigabytes per second) while utilizing only about 3% of the available resources on the Xilinx Virtex UltraScale+ FPGA XCVU9P. On the other hand, the 16 RTB-MAXP engines exhibited somewhat lower throughput and resource utilization, although they did offer a slightly better latency when compared to the CMB-MAXP engines. In the comparison with existing techniques, the CMB-MAXP engine exhibited comparable implementation results in terms of the resource utilization and maximum operating frequency. It is crucial to note that only the proposed engines provide the features of runtime window scalability and boundary padding capability, which are essential requirements for CNN accelerators. The proposed max-pooling engines were employed and tested in our CNN accelerator targeting the CNN model YOLOv4-CSP-S-Leaky for object detection.

Design of CRC circuit for 5G system using VHDL

In this document, we focus on how to design cyclic redundancy check (CRC) circuits with different 5G polynomial divisor using very high-speed integrated circuit (VHSIC) hardware description language (VHDL) to integrate in field-programmable gate array (FPGA) suitable kit using a suitable design code. The different between designed circuits came from the different of data size according to polynomials requirements conditions since there are huge data size in 5G system that required divide it with suitable method and then implemented the required circuit. CRC code as a polar code and short low density parity check (LDPC) is proposed in 5G new radio (NR) systems, CRC properties to divided data and CRC cod make it particularly very useful for codes with higher data rate and longer lengths, and for codes with low data rates and small length as an error detection method. The CRC encoder circuit (transmitter side) and CRC decoder circuit (receiver side) with different polynomial and data size have been designed using VHDL. Xilinx ISE 14.3 simulator, where the test bench simulation results give the expected simulator results of proposed decoding circuit scheme so to integrated using ZYNQ FPGA kit.

Design of CRC circuit for 5G system using VHDL

In this document, we focus on how to design cyclic redundancy check (CRC) circuits with different 5G polynomial divisor using very high-speed integrated circuit (VHSIC) hardware description language (VHDL) to integrate in field-programmable gate array (FPGA) suitable kit using a suitable design code. The different between designed circuits came from the different of data size according to polynomials requirements conditions since there are huge data size in 5G system that required divide it with suitable method and then implemented the required circuit. CRC code as a polar code and short low density parity check (LDPC) is proposed in 5G new radio (NR) systems, CRC properties to divided data and CRC cod make it particularly very useful for codes with higher data rate and longer lengths, and for codes with low data rates and small length as an error detection method. The CRC encoder circuit (transmitter side) and CRC decoder circuit (receiver side) with different polynomial and data size have been designed using VHDL. Xilinx ISE 14.3 simulator, where the test bench simulation results give the expected simulator results of proposed decoding circuit scheme so to integrated using ZYNQ FPGA kit.

FPGA based telecommand system for balloon-borne scientific payloads

Abstract Telecommand (TC) plays a crucial role in the success of high-altitude balloon experiments. Bose, Ray-Chaudhuri, Hocquenghem (BCH) codes are commonly employed to ensure reliable command operation. The Balloon Facility (BF) of Tata Institute of Fundamental Research (TIFR) uses a TC system based on BCH (31,16) coding technique, to control balloon and payload operations. This paper presents prototyping and implementation of TC encoder and decoder using Spartan 6 Field Programmable Gate Array (FPGA). The code is written in Very high-speed integrated circuit Hardware Description Language (VHDL). Simulation and synthesis are done using Xilinx ISE 14.7 design suite. Simulation results show the design is robust. The TC encoder is implemented in a commercial FPGA development board and the TC decoder is implemented in a specially designed FPGA board, successfully. This paper presents the salient features of the TC system in use and the implementation of the system using FPGA.

FPGA-based fault analysis for 7-level switched ladder multi-level inverter using decision tree algorithm

The proposed method involves the fault analysis of the inverter switches present in the multi-level inverter (MLI) circuitry. The decision tree machine learning algorithm is incorporated for the fault analysis of the inverter switches. The multi-level inverter utilized in this work is a 7-level switched ladder multi-level inverter. There is 4 number of switches in the design of a 7-level inverter driven by the non-carrier digital pulse width modulation signals. The non-carried-based digital pulse-width modulator (DPWM) generation is generated using the event angle for the 7-level of the switched ladder inverter. The proposed method investigates the stuck-at-fault occurrences of the 4 switches in the inverter by manipulating the decision tree parameters such as entropy, information gain, and decision tree. Based on the decision tree, the very high-speed integrated circuit hardware description language (VHDL) code is developed by making use of the behavioral modeling and validated for the power, area in the Xilinx Vivado tool. The real-time feasibility is verified for the proposed method by synthesizing the developed VHDL code in the field programmable gate array (FPGA) device.

Convolutional neural network based key generation for security of data through encryption with advanced encryption standard

Machine learning techniques, especially deep learning, are playing an increasingly important role in our lives. Deep learning uses different models to extract information from the data. They have already had a huge impact in areas such as health (i.e., cancer diagnosis), self-driving cars, speech recognition, and data encryption. Recently, deep learning models, including convolutional neural networks (CNN), have been proven to be more effective in the security field. Moreover, the National Institute of Standards and Technology (NIST) recommends the advanced encryption standard (AES) algorithm as the most often utilized encryption method in several security applications. In this paper, a crypt-intelligent system (CIS) capable of securing data is proposed. It is based on the combination of the performance of CNN with the AES, by substituting the key expansion unit of AES with a CNN architecture that performs the key generation. Our CIS is described using very high-speed integrated circuit (VHSIC) hardware description language (VHDL), simulated by ModelSim, synthesized, and implemented with Xilinx ISE 14.7. Finally, the Airtex-7 series XC7A100T device has achieved an encryption throughput of 965.88 Mbps. In addition, the CIS offers a high degree of flexibility and is supported by reconfigurability, based on the experimental results, if sufficient resources are available, the architecture can provide performance that can satisfy cryptographic applications.

Stability analysis of improved combined-mode power converter and power flow control using FPGA

ABSTRACT An improved combined-mode power converter (CMPC) for a solar photovoltaic (SPV) system is presented in this paper. Ten-power electronic switches are utilised for the functioning of the converter. The proposed converter has four modes of operation: buck, boost, inverter, and mixed mode. The new CMPC topology provides a unique and complex switching sequence for implementing the mixed-mode operation. This work uses a field-programmable gate array (FPGA) for mode selection and to create PWM (MS-PWM) signals. A digital MS-PWM controller is configured to switch between improved stepped perturb and observe (ISPO) maximum-power point tracking (MPPT) and sine wave PWM (SPWM). The ISPO provides the appropriate duty cycle for buck/boost operation, while the SPWM controls the inverter operation. This work’s new digital PWM control algorithm supports mode selection, PWM generation, and reconfiguring PWM generation timings. The whole framework for constructing the MS-PWM controller employs a very high-speed integrated circuit hardware description language (VHDL). Simulation and experimental results are presented, proving that the digital MS-PWM controller uses fewer resources with improved accuracy.

Firmware implementation of a recurrent neural network for the computation of the energy deposited in the liquid argon calorimeter of the ATLAS experiment

The ATLAS experiment measures the properties of particles that are products of proton-proton collisions at the LHC. The ATLAS detector will undergo a major upgrade before the high luminosity phase of the LHC. The ATLAS liquid argon calorimeter measures the energy of particles interacting electromagnetically in the detector. The readout electronics of this calorimeter will be replaced during the aforementioned ATLAS upgrade. The new electronic boards will be based on state-of-the-art field-programmable gate arrays (FPGA) from Intel allowing the implementation of neural networks embedded in firmware. Neural networks have been shown to outperform the current optimal filtering algorithms used to compute the energy deposited in the calorimeter. This article presents the implementation of a recurrent neural network (RNN) allowing the reconstruction of the energy deposited in the calorimeter on Stratix 10 FPGAs. The implementation in high level synthesis (HLS) language allowed fast prototyping but fell short of meeting the stringent requirements in terms of resource usage and latency. Further optimisations in Very High-Speed Integrated Circuit Hardware Description Language (VHDL) allowed fulfilment of the requirements of processing 384 channels per FPGA with a latency smaller than 125 ns.

Efficient hardware implementation for lightweight Loong algorithm using FPGA

Recently low-resource devices such as radio frequency identification (RFID), internet of things (IoT), and wireless sensor networks (WSN) using lightweight cryptography (LWC) to protect devices. Created or design low-resource devices with a lightweight cryptographic technique should take into account important factors such as the battery life and the amount of data to be processed. This paper provides a new hardware designed for Loong lightweight cryptographic algorithm that takes into account the previously described constraints. The new hardware architecture for Loong algorithm with resource sharing to reduce system designed. The proposed approach is implemented using ISE Xilinx V14.7 using Virtex 4 field programmable gate array (FPGA) platform. The synthesis analysis for ISE showed the throughput of 851.264 Mbps with efficiency of 2.282 Mbps/slice, and a power consumption of 0.193 Watt. The implementation designed show the all-algorithms size consists of 373 slices, and the maximum possible operating frequency is 212.816 MHz. To the best of our knowledge, this is the first time that Loong algorithm has been implemented on FPGA using very high-speed integrated circuit hardware description language (VHDL).

Study of FIT Dedicated Computer with Dataflow Architecture for High Performance 2-D Magneto-Static Field Simulation

An approach to dedicated computers is discussed in this study as a possibility for portable, low-cost, and low-power consumption high-performance computing technologies. Particularly, dataflow architecture dedicated computer of the finite integration technique (FIT) for 2D magnetostatic field simulation is considered for use in industrial applications. The dataflow architecture circuit of the BiCG-Stab matrix solver of the FIT matrix calculation is designed by the very high-speed integrated circuit hardware description language (VHDL). The operation of the dedicated computer's designed circuit is considered by VHDL logic circuit simulation.

A microsystem design for controlling a DC motor by pulse width modulation using MicroBlaze soft-core

This paper proposes a microsystem based on the field programmable gate arrays (FPGA) electronic board. The preliminary objective is to manipulate a programming language to achieve a control part capable of controlling the speed of electric actuators, such as direct current (DC) motors. The method proposed in this work is to control the speed of the DC motor by a purely embedded architecture within the FPGA in order to reduce the space occupied by the circuit to a minimum and to ensure the reliability of the system. The implementation of this system allows the embedded MicroBlaze processor to be installed side by side with its memory blocks provided by Xilinx very high-speed integrated circuit (VHSIC) hardware description language (VHDL), Embedded C. The control signal of digital pulse-width modulation pulses is generated by an embedded block managed by the same processor. This potential application is demonstrated by experimental simulation on the Vertix5 FPGA chip.

FPGA Implementation of a Chaotic Map with No Fixed Point

The employment of chaotic maps in a variety of applications such as cryptosecurity, image encryption schemes, communication schemes, and secure communication has been made possible thanks to their properties of high levels of complexity, ergodicity, and high sensitivity to the initial conditions, mainly. Of considerable interest is the implementation of these dynamical systems in electronic devices such as field programmable gate arrays (FPGAs) with the intention of experimentally reproducing their dynamics, leading to exploiting their chaotic properties in real phenomena. In this work, the implementation of a one-dimensional chaotic map that has no fixed points is performed on an FPGA device with the objective of being able to reproduce its chaotic behavior as well as possible. The chaotic behavior of the introduced system is determined by estimating the Lyapunov exponents and its chaotic behavior is also analyzed using bifurcation diagrams. Simulations of the system are realized via Matlab, as well as in C and the very high-speed integrated circuit (VHSIC) hardware description language (VHDL). Experimental results on FPGA show that they are like those obtained in the simulations; therefore, this chaotic dynamical system could be used as an element in some encryption schemes such as in the generation of cryptographically secure pseudorandom numbers.

A VHDL Code for Offset Pulse Position Modulation Working with Reed Solomon System by Using ModelSim

Error correction codes, often known as ECC, play a significant part in the process of detecting and correcting data mistakes that occur through communication channels that are unreliable or noisy. The essential concept behind error correction through ECC is to supplement the message that is being sent by the transmitter with redundant bits, the values of which are determined by the parameters n and k. These bits can then be utilized by the receiver to identify and correct specific types of errors. ECC is utilized in a wide variety of applications, including but not limited to data storage, the Internet, and telecommunications. There are numerous variations of ECC, including linear block, convolutional, and turbo codes, among others. The results of a simulation of a linear block reed Solomon, for example, with offset pulse position modulation have been presented in this study. The simulation was carried out in very high-speed integrated circuit hardware description language (VHDL), and a field-programmable gate array was used (FPGA) It made use of a Boolean function to function to program code for an algorithm that is working. Because of its performance, time to market, cost, reliability, and long-term maintenance benefits, FPGA is an appropriate platform for implementing error correction code (ECC). As a part of this project, the technique of offset Pulse Position Modulation (Offset PPM) was invented as an outstanding solution to code the fiber-optic applications and Reed Solomon (RS) codes apply to ModelSim SE-64 10.5 software. In addition, this coding scheme has been approved by the simulation and is matched with theory, and it is expected to be implemented shortly. The study begins with a concise introduction to RS encode/decode about design and performance and then moves on to discuss the development result of simulation and hardware implementation.

VHDL models of the basic dual-rail asynchronous RSFQ gates

This paper presents a basic approach for applying Very High-Speed Integrated Circuits Hardware Description Language (VHDL) descriptions of dual-rail rapid single flux quantum circuits (RSFQ). Because RSFQ is naturally pulsed, dual-rail data encoding encourages event driven data processing at very high speeds. A method for suitable simulation models of the basic asynchronous RSFQ gates is described. The realization of VHDL models is performed in relation with the subsequent implementation for simulation and parameter optimization of complex logic cells.