Very High Speed IC Hardware Description Language Research Articles

FPGA configuration of an alloyed correlated branch predictor used with RISC processor for educational purposes

Instructions pipelining is one of the most outstanding techniques used in improving processor speed; nonetheless, these pipelined stages are constantly facing stalls that caused by nested conditional branches. During the execution of nested conditional branches, the behavior of the running branch depends on the history information of the previous ones; therefore, these branches have the greatest effect in reducing the prediction accuracy of a branch predictor among conditional branches. The purpose of this research is to reduce the stall cycles caused by correlated branches misprediction by introducing a hardware model of a branch predictor that combines both local and global prediction techniques. This predictor integrates the prediction characteristics of the alloyed predictor with those of the correlated predictor. the predictor design which implemented in VHDL (Very high-speed IC hardware description language) was inserted in previously designed MIPS (microprocessor without interlocked pipelined stages) processor and its prediction accuracy was confirmed by executing a program using the selection sort algorithm to sort 100 input numbers of different combinations ascendingly.

FPGA-realization of an RBF-NN tuning PI controller for sensorless PMSM drives

The estimation and control of the rotor position for sensorless permanent magnet synchronous motor (PMSM) drives based on extended Kalman filter (EKF) and artificial neural network (ANN) is presented in this paper. The EKF is a rotor position estimator which is a full-order stochastic observer for the recursive optimum state estimation of a nonlinear dynamic system in real time by using signals that are in the noisy environment. An ANN constructed by radial basis function neural network (RBFNN) and a parameter adjustable mechanism is applied to speed control loop of the PMSM drives to cope with the effect of the system dynamic uncertainty and external load. In this paper, firstly, a mathematical model for PMSM is derived, and a sensorless FOC is built up. Secondly, the rotor position and rotor speed which are estimated by using EKF is described. These estimated values are feed-backed to the current loop for FOC and to the speed loop for RBFNN-based self-tuning PI control. Thirdly, a very high-speed IC hardware description language (VHDL) is presented to describe the behavior of the adopted control and estimation algorithm. Fourthly, to verify the correctness of the designed VHDL code of the control and the estimation algorithm, based on electronic design automation (EDA) simulator link, a co-simulation work is constructed by Simulink and ModelSim. And some simulation results verify the correctness and effectiveness. Finally, an experimental system with a PMSM, a motor driver circuit, and a field programmable gate array (FPGA) board are set up to implement the proposed rotor position estimation and speed control algorithm.

FPGA-realization of the kinematics IP for SCARA robot

In the implementation of robot motion control, it often requires complex forward and inverse kinematics calculation. However, this algorithm requires more CPU time in the software realization and apparently affects the response of robot movement. To solve this problem, the work is aimed at the development of the forward and inverse kinematics IP (intellectual property) based on FPGA (field programmable gate array) implementation and hoped to complete the overall computation less than ten microseconds for the purpose of enhancing the performance of the robot movement. In this paper, firstly, the forward and inverse kinematics for SCARA robot is derived. Secondly the circuit behavior using VHDL (Very-High-Speed-IC Hardware Description Language) is described. The design of VHDL code will apply the parameterized function to increase the code flexible and the FSM (Finite state machine) strategy is used to reduce the hardware resource usage. To verify the correctness of the proposed forward and inverse kinematics IP, a co-simulation work is constructed by ModelSim and Simulink. The forward and inverse kinematics IP is run by ModelSim and the Simulink models is taken as a test bench that generates stimulus to ModelSim and displays the output response. Finally, the developed forward and inverse kinematics IP will be downloaded to FPGA to further confirm its effectiveness.

FPGA-realization of a sensorless speed controller for PMSM drives using novel sliding mode observer

FPGA-realization of a rotor position estimation algorithm based on a novel sliding mode observer (SMO) for permanent magnet synchronous motor (PMSM) drives is adopted in this paper. Comparing to the conventional SMO, the estimator based on the novel SMO is presented for reducing the chattering phenomenon and improving the estimated precision of the rotor position. However, a hybrid sensorless control system for PMSM drives using I-f startup method then a smooth transition to the novel SMO-based sensorless field oriented control (FOC) are also considered in this paper. In realization, a very high speed IC hardware description language (VHDL) is firstly introduced to describe the behavior of the adopted estimation and control algorithm which is called the sensorless control intellectual property (IP). Then, to verify the correctness of the designed VHDL code for the sensorless control IP, it will be downloaded to the FPGA, and an experimental system with a sensorless PMSM drive is set up and some experimental results are demonstrated.

FPGA-realization of a speed control IC for induction motor drive

Purpose – The purpose of this paper is to integrate the function of a speed controller for induction motor (IM) drive, such as the speed PI controller, the current vector controller, the slip speed estimator, the space vector pulse width modulation scheme, the quadrature encoder pulse, and analog to digital converter interface circuit, etc. into one field programmable gate array (FPGA). Design/methodology/approach – First, the mathematical modeling of an IM drive, the field-oriented control algorithm, and PI controller are derived. Second, the very high speed IC hardware description language (VHDL) is adopted to describe the behavior of the algorithms above. Third, based on electronic design automation simulator link, a co-simulation work constructed by ModelSim and Simulink is applied to verify the proposed VHDL code for the speed controller intellectual properties (IP). Finally, the developed VHDL code will be downloaded to the FPGA for further control the IM drive. Findings – In realization aspect, it only needs 5,590 LEs, 196,608 RAM bits, and 14 embedded 9-bit multipliers in FPGA to build up a speed control IP. In computational power aspect, the operation time to complete the computation of the PI controller, the slip speed estimator, the current vector controller are only 0.28 μs, 0.72 μs, and 0.96 μs, respectively. Practical implications – Fast computation in FPGA can speed up the speed response of IM drive system to increase the running performance. Originality/value – This is the first time to realize all the function of a speed controller for IM drive within one FPGA.

Digital hardware implementation of a radial basis function neural network

This work studies a digital hardware implementation of a radial basis function neural network (RBF NN) Firstly, the architecture of the RBF NN, which consists of an input layer, a hidden layer of nonlinear processing neurons with Gaussian function, an output layer and a learning mechanism, is presented. The supervising learning mechanism based on the stochastic gradient descent (SGD) method is applied to update the parameters of RBF NN. Secondly, a very high-speed IC hardware description language (VHDL) is adopted to describe the behavior of the RBF NN. The finite state machine (FSM) is applied for reducing the hardware resource usage. Thirdly, based on the electronic design automation (EDA) simulator link, a co-simulation work by Simulink and ModelSim is applied to verify the VHDL code of RBF NN. Finally, some simulation cases are tested to validate the effectiveness of the proposed digital hardware implementation of the RBF NN.

Design and Implementation of a Microprocessor-Based PI Controller for PMSM Drives

This work presents a hardware implementation of a simple microprocessor; then uses this microprocessor to design a PI controller for PMSM (Permanent Magnet Synchronous Motor) drives. In this paper, firstly, the mathematical model of PMSM drives is illustrated. Secondly, the architecture of a simple microprocessor based on RTL (Register Transfer Level) method is proposed and the VHDL (Very high speed IC Hardware Description Language) is adopted to describe the behavior of the simple microprocessor. Thirdly, a machine code of PI controller based on the proposed simple microprocessor is designed. Finally, a co-simulation by Simulink/ModelSim is applied and verified the performance of the microprocessor-based PI controller.

Design and simulation of a sensorless permanent magnet synchronous motor drive with microprocessor-based PI controller and dedicated hardware EKF estimator

In this study, we propose a digital hardware implementation of a speed controller for a sensorless permanent magnet synchronous motor (PMSM) drive. First, the extended Kalman filter (EKF) is used to estimate the rotor flux angle (FA) and rotor speed. The estimated rotor FA is sent back to the current loop for vector control and the estimated rotor speed is fed back into the speed loop for closed-loop speed control. A PI controller is utilized in the speed loop control process. Second, we propose the architecture of a simple microprocessor based on the register transfer level method and we design machine code for the PI controller based on the proposed simple microprocessor. Third, the current vector controller and the EKF algorithm are implemented in dedicated hardware and the finite state machine method is used to design the computational process. Fourth, the Very high speed IC Hardware Description Language (VHDL) is employed to describe the behaviors of the simple microprocessor, the current vector controller, and the EKF algorithm. Finally, a co-simulation study was performed using Simulink and Modelsim to evaluate the effectiveness and correctness of the proposed system, and we present some simulated cases.

FPGA-based hardware implementation of arctangent and arccosine functions for the inverse kinematics of robot manipulator

Purpose– The inverse kinematics in robot manipulator have to handle the arctangent and arccosine function. However, the two functions are complicated and need much computation time so that it is difficult to be realized in the typical processing system. The purpose of this paper is to solve this problem by using Field Programmable Gate Array (FPGA) to speed up the computation power.Design/methodology/approach– The Taylor series expansion method is firstly applied to transfer arctangent and arccosine function to a polynomial form. And Look-Up Table (LUT) is used to store the parameters of the polynomial form. Then the behavior of the computation algorithm is described by Very high-speed IC Hardware Description Language (VHDL) and a co-simulation using ModelSim and Simulink is applied to evaluate the correctness of the VHDL code.Findings– The computation time of arctangent and arccosine function using by FPGA need only 320 and 420 ns, respectively, and the accuracy is <0.01°.Practical implications– Fast computation in arctangent and arccosine function can speed up the motion response of the real robot system when it needs to perform the inverse kinematics function.Originality/value– This is the first time such to combine the Taylor series method and LUT method in the computation the arctangent and arccosine function as well as to implement it with FPGA.

FPGA IMPLEMENTATION OF A FUNCTIONAL MICROCONTROLLER

In any control and controller system applications, microcontroller is an important module, which provides the control, timing and status signals. A microprocessor is usually defined as “a single chip that contains control logic and data processing logic, so that it can execute instructions listed in a program to operate on some data”. Microcontrollers are nothing but microprocessors with onchip memory. This paper primarily deals with the implementation of an 8 bit microcontroller to perform arithmetic and logical operations. The modules are programmed using Very High Speed IC Hardware Description Language (VHDL). Using top-down approach, the elements of the microcontroller are identified as basic registers, instruction register, program counter, ALU, ROM, Control and timing Unit. All these modules are connected together to form a top module which is controlled by a Finite State Machine (FSM). The Finite State Machine enters each of the predefined states based on the inputs. FSM implementation also aids in changing the functionalities of the system without completely redesigning the system. Finally, in the top level module, these blocks are connected to form a functional microcontroller. In this paper, we have simulated and synthesized the various parameters of microcontroller by using VHDL on Xilinx ISE 8.2i and SPARTAN 3 FPGA board.

FPGA-Realization of Vector Control for PMSM Drives

The design and implementation of a vector control for Permanent Magnetic Synchronous Motor (PMSM) based on Field Programmable Gate Array (FPGA) technology is presented in this paper. Firstly, a Space Vector Pulse Width Modulation (SVPWM) scheme, vector control method and PI controller are derived. Secondly, the Very-High-Speed IC Hardware Description Language (VHDL) is adopted to describe the behavior of the aforementioned control algorithms. Finally, an experimental system is setup to evaluate the effectiveness and correctness of the proposed vector controller for PMSM drives.

Hardware Design and Simulation of Reduced-Order Extended Kalman Filter Estimator and Speed Fuzzy Controller for Sensorless PMSM Drives

The design and co-simulation of a sensorless control for permanent magnet synchronous motor (PMSM) drive is presented in this paper. Firstly, the block diagram of vector control and fuzzy algorithm are designed. Secondly, a flux position and speed of rotor are estimated through the reduced-order extended kalman filter (EKF). Thirdly, the very-high-speed IC hardware description language (VHDL) is adopted to describe the behavior of all functions of the system. Fourthly, the simulation work is performed by MATLAB/Simulink and ModelSim co- simulation mode. The PMSM, inverter and speed command are performed in Simulink and the sensorless speed control of PMSM drive is executed in ModelSim. Finally, the comparison results between PI and Fuzzy controller validate the effectiveness of the sensorless PMSM speed control system. It has fast reacting speed and good dynamic performance. 

FPGA Realization of Sensorless PMSM Speed Controller Based on Extended Kalman Filter

Based on extended Kalman filter (EKF), the design and FPGA implementation of a sensorless control intellectual property (IP) for permanent magnet synchronous motor (PMSM) drive are presented in this paper. Firstly, the mathematical model for PMSM is derived and the vector control is built up. Secondly, the rotor flux angle (FA) and rotor speed which are estimated by using EKF are described. These estimated values are feedbacked to the current loop for vector control and to the speed loop for speed control. Thirdly, the very-high-speed IC hardware description language (VHDL) is adopted to describe the behavior of the sensorless speed control IP which includes the circuits of space vector pulse width modulation (SVPWM), coordinate transformation, EKF, and PI controller. Finally, to evaluate the effectiveness and correctness of the proposed of system, a cosimulation work performed by Simulink and ModelSim is firstly conducted. Then, an experimental system by FPGA chip and motor driving board is set up to further validate the performance of the proposed EKF-based sensorless speed control IP.

Optimized FPGA design, verification and implementation of a neuro-fuzzy controller for PMSM drives

The work presents a neural fuzzy controller (NFC) for speed loop of permanent synchronous motor (PMSM) drives based on the technology of field programmable gate array (FPGA). Firstly, a mathematic model of the PMSM drive is derived; then to increase the performance of the PMSM drive system, a fuzzy controller (FC) which its parameters are adjusted by a radial basis function neural network (RBF NN) is applied to the speed controller for coping with the effect of the system dynamic uncertainty. Secondly, very high speed IC hardware description language (VHDL) is adopted to describe the behavior of the speed controller of PMSM drives which includes the circuits of space vector pulse width modulation (SVPWM), coordinate transformation, NFC, etc. Besides, to reduce the resource usage while implementing in field programmable gate array (FPGA), a sequential execution using finite state machine (FSM) is applied. Thirdly, based on electronic design automation (EDA) simulator link, a simulation work is constructed by MATLAB/Simulink and ModelSim co-simulation mode which the PMSM, inverter and speed command are performed in Simulink as well as the speed controller of PMSM drives is executed in ModelSim. Finally, some co-simulation results validate the effectiveness of the proposed NFC-based speed controller for PMSM drives.

Simulink/Modelsim Co-Simulation and FPGA Realization of Speed Control IC for PMSM Drive

PMSM (Permanent Magnetic Synchronous Motor) has been increasingly used in many high performance application due to its advantages of high power density, high power factor and efficiency. The design and implementation of a fuzzy-control based speed control IC for PMSM from Simulink/Modelsim co-simulation to FPGA (Field Programmable Gate Array) realization is presented in this paper. Firstly, a SVPWM scheme, vector control method and fuzzy controller are derived and applied in the speed control IC of PMSM drive. Secondly, the Very-High-Speed IC Hardware Description Language (VHDL) is adopted to describe the behavior of the aforementioned control algorithms. To evaluate the effectiveness and correctness of the proposed speed control IC, a co-simulation work performed by Matlab/Simulink and Modelsim is firstly conducted. Then, an experimental system by FPGA chip, Nios processor and motor driving board is set up to further validate the performance of the proposed speed control IC. Finally, the results in simulation and in experiment will be compared and discussed.

Reconciling conflicting design-automation standards

There are four incompatible sets of guidelines for describing and communicating data for products ranging from components to systems. Representatives from the bodies governing the various standards have been trying to decide how to make the standards work together, a process they call harmonization. The standards involved are the Electronic Design Interchange Format (EDIF), the Initial Graphics Exchange Specification (IGES), some standards developed by the Institute for Interconnecting and Packaging Electronic Circuits (IPC), and the Very High-Speed IC Hardware Description Language (VHDL). A subcommittee has been set up, under the sponsorship of the American National Standards Institute, to bring about the harmonization. The tasks facing the subcommittee are examined.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>