Vertical Power DMOSFETs Research Articles

High current capability of 3C-SiC vertical DMOSFETs

Vertical power DMOSFETs in 3C-SiC, ranging in size from a single-cell to 3 × 3 mm 2 containing 12,000 hexagonal cells, were developed for the first time. Both the drain and leakage currents scale linearly with device size up to a 1 × 1 mm 2 device containing 976 cells. An inversion channel mobility of 40 cm 2/V · s and interface state density of 5 × 10 12 to 1 × 10 13 cm −2 eV −1 were obtained. A fabricated DMOSFET with a gate length of 2 μm had a low specific on-resistance of 5.6 mΩ · cm 2 for a single-cell device. A current density of 1220 A/cm 2 for a single-cell device, and 380 A/cm 2 for a 102-cell device were demonstrated. A high current capability of 41 to 132 A at 600 V can be extrapolated for a 3 × 3 mm 2 chip.

A Self-Aligned Process for High-Voltage, Short-Channel Vertical DMOSFETs in 4H-SiC

In this paper, we describe a self-aligned process to produce short-channel vertical power DMOSFETs in 4H-SiC. By reducing the channel length to /spl les/0.5 /spl mu/m, the specific on-resistance of the MOSFET channel is proportionally reduced, significantly enhancing performance.

Self-Aligned Short-Channel Vertical Power DMOSFETs in 4H-SiC

Self-Aligned Short-Channel Vertical Power DMOSFETs in 4H-SiC

Dynamics of power MOSFET switching under unclamped inductive loading conditions

The parasitic bipolar transistor inherent in a vertical power DMOSFET structure can have a significant impact on its reliability. Unclamped Inductive Switching (UIS) tests were used to examine the reliability of DMOSFET's in extremely harsh switching conditions. The reliability of a power DMOSFET under UIS conditions is directly related to the amount of avalanche energy the device can survive. A number of DMOSFET structures were critically examined under UIS conditions to determine the impact of bipolar transistor parameters on device reliability. The UIS dynamics were studied based on the results obtained from an advanced mixed device and circuit simulator in which the internal carrier dynamics were evaluated under boundary conditions imposed by the circuit operation. It is shown that premature open base bipolar transistor breakdown can occur when the p-base sheet resistance is high. A device structure with a shallow self-aligned p/sup +/ region is shown to prevent the parasitic bipolar turn-on and avoid premature UIS breakdown without compromising the power-switching efficiency. The simulation results are shown to be in excellent agreement with the measured data under a wide range of inductive loading conditions.

A high-density, self-aligned power MOSFET structure fabricated using sacrificial spacer technology

A novel power MOSFET structure fabricated using sacrificial spacer technology is described. Anisotropically etched sidewall oxide spacers were used to implement self-aligned shallow p/sup +/ surface diffused regions to reduce the p-base sheet resistance and its contact resistance. Vertical power DMOSFETs with V/sub DB/=150 V and R/sub sp/=9.7 m Omega -cm/sup 2/ were fabricated using this technology, where V/sub DB/ is the drain-source avalanche breakdown voltage and R/sub sp/ is the specific on-state resistance. The measured on-state resistance performance is a factor of 4 times smaller compared to commercially available power MOSFETs in the 150-V reverse blocking range.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Effect of p-base sheet and contact resistances on static current-voltage characteristics of scaled low-voltage vertical power DMOSFETs

Static current-voltage characteristics of low-voltage scaled power double-diffused MOSFETs fabricated using selectively formed TiSi/sub 2/ films on gate polysilicon and source contact regions are reported. It is shown that considerable modulation of drain-source current-voltage characteristics results from increased p-base sheet and contact resistances. This effect is found to vanish at higher operating temperatures. Increased p-base contact resistance also results in a large forward voltage drop for the body p-n junction diode. >

Interelectrode capacitance nonlinearities in vertical power DMOSFETs

Extensive numerical simulations were performed to understand interelectrode capacitance characteristics of vertical power DMOSFETs. Two-dimensional simulations indicate large capacitance-voltage nonlinearities, especially for the gate-to-drain Miller capacitance Cgd. Capacitance-voltage characteristics are explained in terms of a simple equivalent circuit that relates each capacitance component to its physical origin.

Optimally scaled low-voltage vertical power MOSFETs for high-frequency power conversion

The systematic optimization of low-voltage silicon power MOSFET technology is described. It is shown that device scaling using advanced fabrication technologies can result in nearly optimal performance from low-voltage silicon power MOSFETs. The details discussed include: (1) system impact; (2) unit cell optimization; (3) device and process modeling; (4) fabrication technology development; and (5) performance results. The device technologies optimized include 30-, 50-, and 100-V vertical power DMOSFETs with optimally scaled gate polysilicon and source/drain contacts. Devices with the lowest specific on-resistance, the lowest specific input capacitance, and improved high-frequency switching performance have been fabricated with excellent wafer yield. This is the first successful demonstration of device scaling and its impact on performance of high-voltage and smart-power technologies.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Monolithically integrated power MOSFET and Schottky diode with improved reverse recovery characteristics

A power DMOSFET structure with a monolithically integrated Schottky diode located under the source contact pad is described. In this structure the source contact metallization step is also used to fabricate an epitaxial drift region Schottky diode in parallel with the parasitic body p-n junction diode of the power MOSFET. Such a structure results in significantly improved internal diode switching characteristics with no degradation in the on-state resistance and drain-source breakdown voltage. The integral power MOSFET technology was used to fabricate 30- and 45-V vertical power DMOSFETs with a reduction in peak reverse current and stored charge of more than 25% as compared to a conventional power DMOSFET. The Schottky diode consumed less than 15% of the active transistor area.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Selectively silicided vertical power DMOSFETs for high-frequency power conversion

A 50 V, 056mΩcm2 vertical power DMOSFET fabricated using selectively silicided gate and source contact regions is reported. The gate-source isolation was provided by anisotropically etched oxide sidewall spacers. This new device structure lowers the source contact resistance considerably by providing a larger contact area and improves the distributed gate RC propagation delay by lowering the gate sheet resistance compared with the conventional heavily doped n+-polysilicon gates. Devices with cell density as high as 8 million cells/inch2 and die size as large as 200 mil × 220 mil and capable of conducting more than 160 A of current have been successfully fabricated with excellent gate yield. These results represent the highest reported forward conductivities for any type of power FET in the 50 V reverse blocking range