Vertical Gate NAND Research Articles

Increased memory performance of a Pi (Φ) gate structure in a 3-D stackable vertical gate NAND flash memory

In this study, we propose a pi(Φ)-gate structure that improves the performance of vertical gate (VG) NAND flash memory structures. The pi-gate (PG) structure extends the gates along the top and the bottom surfaces of the silicon layer, widening the channel width and resulting in an increased device current. The extended gates also enhance gate coupling with the channel by allowing more of the gate field to interact with the channel, giving lower threshold voltages (20% reduction) and lower subthreshold swings (21% reduction) and greatly enhancing the switching characteristics. Also, a PG width of 18 nm resulted in an increase in the programmed threshold voltage shift of 39% compared to that of the conventional VG-NAND structure. The PG structured VG-NAND may allow a non-volatile memory to be further integrated by giving solutions to the high channel resistance and reduced memory performance issues related to integration in vertical dimensions.

Reduce Cell to Cell Charge Interference by Virtual Ground Inclusion in 3-Dimensional Vertical Gate NAND Flash Memory

In this work, we propose a structural modification to the 3-dimensional vertical gate NAND flash memory that will reduce the charge interference caused by stored charge on the opposite facing cell. In the barrier oxide structure (BOS), an oxide layer was inserted into the center of the body to physically block the conduction electrons moving to and from the channel regions influenced by the charge stored on either of the Oxide-Nitride-Oxide (ONO) trap layers. In the virtual ground structure (VGS), a highly p-type doped poly silicon layer was inserted to act as a virtual ground to reduce the electric-field changes caused by the stored change on the ONO trap layers. We investigated the I-V characteristics of the different structures using 3-D TCAD simulation tool, depending on the body type (crystalline or poly silicon) at double programming and single programming. We confirmed that the charge interference problem was reduced significantly by the BOS and VGS modifications in the crystalline silicon and high quality poly silicon body structures.