Vertical Feedthrough Research Articles

Research on a 3D Encapsulation Technique for Capacitive MEMS Sensors Based on Through Silicon Via.

A novel three-dimensional (3D) hermetic packaging technique suitable for capacitive microelectromechanical systems (MEMS) sensors is studied. The composite substrate with through silicon via (TSV) is used as the encapsulation cap fabricated by a glass-in-silicon (GIS) reflow process. In particular, the low-resistivity silicon pillars embedded in the glass cap are designed to serve as the electrical feedthrough and the fixed capacitance plate at the same time to simplify the fabrication process and improve the reliability. The fabrication process and the properties of the encapsulation cap were studied systematically. The resistance of the silicon vertical feedthrough was measured to be as low as 263.5 mΩ, indicating a good electrical interconnection property. Furthermore, the surface root-mean-square (RMS) roughnesses of glass and silicon were measured to be 1.12 nm and 0.814 nm, respectively, which were small enough for the final wafer bonding process. Anodic bonding between the encapsulation cap and the silicon wafer with sensing structures was conducted in a vacuum to complete the hermetic encapsulation. The proposed packaging scheme was successfully applied to a capacitive gyroscope. The quality factor of the packaged gyroscope achieved above 220,000, which was at least one order of magnitude larger than that of the unpackaged. The validity of the proposed packaging scheme could be verified. Furthermore, the packaging failure was less than 1%, which demonstrated the feasibility and reliability of the technique for high-performance MEMS vacuum packaging.

A method for wafer level hermetic packaging of SOI-MEMS devices with embedded vertical feedthroughs using advanced MEMS process

This paper presents a novel, inherently simple, and low-cost fabrication and hermetic packaging method developed for SOI-MEMS devices, where a single SOI wafer is used for the fabrication of MEMS structures as well as vertical feedthroughs, while a single glass cap wafer is used for hermetic encapsulation and routing metallization. Hermetic encapsulation can be achieved either with the silicon-glass anodic or Au–Si eutectic bonding techniques. The dies sealed with anodic and Au–Si eutectic bonding provide a low vertical feedthrough resistance around 50 Ω. Glass-to-silicon anodically and Au–Si eutectic bonded seals yield a very stable cavity pressure below 10 mTorr with thin-film getters, which are measured to be stable even after 311 d. The package pressure can be adjusted from 5 mTorr to 20 Torr by using different outgassing, cavity depth, and gettering options. The packaging yield is observed to be around 64% and 84% for the anodic and Au–Si eutectic packages, respectively. The average shear strength of the anodic and eutectic packages is measured to be higher than 17 MPa and 42 MPa, respectively. Temperature cycling, high temperature storage, and ultra-high temperature shock tests result in no degradation in the hermeticity of the packaged chips, proving perfect thermal reliability.

Hermetic Electrical Feedthroughs Based on the Diffusion of Platinum into Silicon

Within this paper a novel approach for the development of hermetic electrical feedthroughs is introduced. So far, every vertical feedthrough induces at the feedthroughs' interfaces possible paths for water to leak across the hermetic barrier into the hermetic package. The presented approach is based on the diffusion of platinum into silicon, locally changing the electrical behavior of the substrate due to the induced impurities. This method avoids destroying the bulk material, in this case silicon, preserving the hermetic barrier environment. Different n-type silicon substrates were investigated for their usability through various diffusion experiments under two gas atmospheres: Argon/hydrogen and pure nitrogen. A significant change in silicon behavior could be shown for one of the used substrates. The current flowing through the bulk could be decreased by a factor of around 12 for an argon/hydrogen atmosphere and by around 10 for pure nitrogen. The current directly correlates with a local increase of the substrates' resistance, demonstrating the possibility of adapting the electrical properties of a substrate to create insulating areas within a conductive substrate.

A Method of Fabricating Vacuum Packages with Vertical Feedthroughs in a Wafer Level Anodic Bonding Process

Abstract This paper presents a new method for wafer level vacuum packaging of MEMS devices using anodic bonding together with vertical feedthroughs formed on an SOI cap wafer, eliminating the need for any sealing material or any complex via-refill or trench-refill vertical feedthrough steps. The packaging yield is experimentally verified to be above 95%, and the cavity pressure is characterized to be as low as 1 mTorr with the help of a thin-film getter. The shear strength of several packages is measured to be above 15 MPa.

Design and fabrication of high performance wafer-level vacuum packaging based on glass–silicon–glass bonding techniques

In this paper, a high performance wafer-level vacuum packaging technology based on GSG triple-layer sealing structure for encapsulating large mass inertial MEMS devices fabricated by silicon-on-glass bulk micromachining technology is presented. Roughness controlling strategy of bonding surfaces was proposed and described in detail. Silicon substrate was thinned and polished by CMP after the first bonding with the glass substrate and was then bonded with the glass micro-cap. Zr thin film was embedded into the concave of the micro-cap by a shadow-mask technique. The glass substrate was thinned to about 100 µm, wet etched through and metalized for realizing vertical feedthrough. During the fabrication, all patterning processes were operated carefully so as to reduce extrusive fragments to as little as possible. In addition, a high-performance micro-Pirani vacuum gauge was integrated into the package for monitoring the pressure and the leak rate further. The result shows that the pressure in the package is about 120 Pa and has no obvious change for more than one year indicating 10−13 stdcc s−1 leak rate.

A Wafer-Level Vacuum Package Using Glass-Reflowed Silicon Through-Wafer Interconnection for Nano/Micro Devices

We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging.

Design and consideration of wafer level micropackaging for distributed RF MEMS phase shifters

A novel packaging structure which is performed using wafer level micropackaging on the thin silicon substrate as the distributed RF MEMS phase shifters wafer with vertical feedthrough is presented. The influences of proposed structure on RF performances of distributed RF MEMS phase shifters are investigated using microwave studio (CST). Simulation results show that the insertion loss (S21) and return loss (S11) of packaged MEMS phase shifters are −0.4–1.84 dB and under −10 dB at 1–50 GHz, respectively. Especially, the phase shifts have well linear relation at the range 1–48 GHz. At the same time, this indicated that the proposed pacakaging structure for the RF MEMS phase shifter can provide the maximum amount of linear phase shift with the minimum amount of insertion loss and return loss of less than −10 dB.

Ultrathin Silicon Micropackaging for RF MEMS Devices

In this paper we report a technology for lightweight, small radio-frequency (rf) microelectromechanical system packaging with a short electrical path length. We used an ultrathin silicon substrate as the packaging substrate. Via holes for vertical feed-through were fabricated on the thin silicon wafer. Then, bottom-up gold electroplating was applied to fill via holes. For hermetic sealing, gold-gold direct metal bonding was used in the sealing line. The packaged rf device has a reflection loss below -22 dB and an insertion loss of -0.05 to -0.08 dB. Therefore, with the ultrathin silicon wafer, a lightweight, small device package can be constructed.

Ultra Thin 실리콘 웨이퍼를 이용한 RF-MEMS 소자의 웨이퍼 레벨 패키징

In this paper, we report a novel RF-MEMS packaging technology with lightweight, small size, and short electric path length. To achieve this goal, we used the ultra thin silicon substrate as a packaging substrate. The via holes lot vortical feed-through were fabricated on the thin silicon wafer by wet chemical processing. Then, via holes were filled and micro-bumps were fabricated by electroplating. The packaged RF device has a reflection loss under 22 〔㏈〕 and a insertion loss of -0.04∼-0.08 〔㏈〕. These measurements show that we could package the RF device without loss and interference by using the vertical feed-through. Specially, with the ultra thin silicon wafer we can realize of a device package that has low-cost, lightweight and small size. Also, we can extend a 3-D packaging structure by stacking assembled thin packages.

수직형 Feed-through 갖는 RF-MEMS 소자의 웨이퍼 레벨 패키징

수직형 Feed-through 갖는 RF-MEMS 소자의 웨이퍼 레벨 패키징

Development of microwave multilayer plastic-based multichip modules

We present the design and development of multilayer plastic-based multichip modules (MCM) at microwave frequencies. A vertical feed-through interconnect, which consists of embedded copper wires in plastic, has been developed to transport RF/microwave and dc signals from the first to the second packaging level. The development of this vertical feed-through enables plastic modules to be configured in a surface mount topology that can be interfaced with low cost FR-4 boards using ball grid arrays (BGA). The experimental analysis results demonstrate that this vertical feed-through used with BGAs has ultra-low parasitics and achieves a return loss of greater than 20-dB at 4-GHz. In addition, we demonstrate a number of packaged active microwave circuits including a switch, a low noise amplifier (LNA) and a power amplifier using the plastic module technology at microwave frequencies.