Vertical-channel Field-effect Transistors Research Articles

Study on self-heating effect and lifetime in vertical-channel field effect transistor

In this paper, self-heating effect in newly introduced Vertical channel Field Effect Transistors (VFETs) is investigated and discussed, and several architecture parameters such as channel width, number of channels affecting thermal reliability of VFET are studied through simulations. In addition, a study on the change of thermal properties is conducted when air gap/spacer is used to reduce the influence of the parasitic capacitance. It is illustrated that VFET shows high lattice temperature and thermal resistance increase from changes in such architecture parameters, air gap in BEOL (Back End of Line), and air spacers. Additionally, the lattice temperature imbalance between channels can be mitigated by adjusting the inter-channel spacing of a multi-channel VFET.

Surrounding Gate Vertical-Channel FET With a Gate Length of 40 nm Using BEOL-Compatible High-Thermal-Tolerance In-Al-Zn Oxide Channel

We have demonstrated, for the first time, a surrounding gate vertical-channel field-effect transistor (FET) with a gate length of 40 nm by introducing back-end-of-line (BEOL) process-compatible oxide semiconductor (OS) In-Al-Zn-O as a channel material. Fabricated FETs exhibited high scalability by excellent thermal stability (~420 °C) compared to conventional In-Ga-Zn-O-channel FETs, with high-mobility (12.7 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V.s) characteristics. Furthermore, the vertical-channel FET also exhibited excellent reliability and stable operation without floating body effect. Endurance of over 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> cycles was also demonstrated. Our work opens a pathway to realization of high-performance BEOL transistor for 3-D-large-scale integration (LSI) applications.

A novel buried grid device fabrication technology

A new buried grid fabrication technology based upon preferential etching and planar epitaxial refill techniques is described. This technology produces buried grids with a rectangular cross-section. The resulting improvement in the aspect ratio of the channel between the grids allows the fabrication of large area, high voltage, vertical channel field effect transistors and field controlled thyristors with very high blocking gains.