Vertical Bus Research Articles

Echelle grating based mode demultipexer for vertical mode-division multiplexing.

We have proposed a mode multi/demultiplexer based on the echelle grating suitable for vertical multimode bus waveguide. Compared with the lateral multimode waveguide, the vertical scheme has much smaller bending radius which leads to compact system size. The guided modes in the multimode waveguide are able to be separated simultaneously by the echelle grating since they experiences different propagation constants in the free propagation region. Due to the high performance of the grating itself, the theoretical modal crosstalk can be as low as around -40dB. Moreover, we demonstrate the possibility to integrate WDM together with MDM by using only one echelle grating, which is favorable in real applications considering the compact system setup and simple design rules.

Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces

Wireless 3-D network-on-chips (NoCs) with inductive-coupling ThruChip interfaces provide a large degree of flexibility for customizing the number of arbitrary chips in a package after chips have been fabricated. To simplify the vertical communication interfaces, static time division multiple access (TDMA) is used for the vertical broadcast buses, while arbitrary or customized topologies can be used for the intrachip network. This paper proposes two techniques to break through the simple static TDMA-based vertical buses while maintaining a simple communication interface. The first technique is headfirst sliding (HS) routing to reduce the waiting time for acquiring the communication time-slot. HS routing selects the best vertical bus based on the current time, taking advantage of static TDMA. The second technique extends carrier sense multiple access with collision detection (CSMA/CD) for vertical broadcast buses. We introduce a packet collision detection technique for inductive-coupling buses and propose two retransmission strategies to reduce the waiting time for packet retransmissions caused by collisions. Network simulation results show that HS routing reduces the communication latency by 39.1% compared with the conventional static TDMA bus-based 3-D NoC that uses the shortest path routing. The proposed CSMA/CD bus also improves the latency by 52.5% and throughput by 34.1%. The full-system simulation results show that HS routing and the proposed CSMA/CD technique reduce the application execution time accordingly while maintaining the average flit transfer energy overhead modest.

The Effects of System Grounding, Bus Insulation, and Probability On Arc Flash Hazard Reduction—Part 2: Testing

This paper provides a follow-up to the paper The Effects of System Grounding, Bus Insulation and Probability on Arc Flash Hazard Reduction—The Missing Links . In that paper, system grounding and bus insulation were considered a means of reducing the probability of an arc flash incident by approximately two orders of magnitude. In September 2013, additional testing was conducted on a low-voltage motor control center (LVMCC) with the expectation that engineering enhancements such as insulated vertical bus, high resistance grounding, and other techniques could be implemented to further reduce the probability of an arc flash incident. The testing performed was with faults initiated in locations typically found in operating petrochemical facilities, in LVMCCs, with the starter unit door open. This paper discusses the findings of testing on real-world electrical equipment in an effort to further understand and minimize the probability of an arc flash incident. This paper reviews the physics of the arcing fault and how ignition wire, geometry, and the number of anode/cathode pairs all contribute to arcing fault energy and personnel exposure.

3D NoC with Inductive-Coupling Links for Building-Block SiPs

A wireless 3D NoC architecture is described for building-block SiPs, in which the number of hardware components (or chips) in a package can be changed after chips have been fabricated. The architecture uses inductive-coupling links that can connect more than two examined dies without wire connections. Each chip has data transceivers for the uplink and downlink in order to communicate with its neighboring chips in the package. These chips form a vertical unidirectional ring network so as to fully exploit the flexibility of the wireless approach that enables us to add, remove, and swap the chips in the ring. To avoid protocol and structural deadlocks in the ring, we use bubble flow control, which does not rely on the conventional VC-based deadlock avoidance mechanism. In addition, we propose a bidirectional communication scheme to form a bidirectional ring network by using the inductive-coupling transceivers that can dynamically change the communication modes, such as TX, RX, and Idle modes. This paper illustrates the inductive-coupling transceiver circuits, which can carry high data transfer rates of up to 8 Gbps per channel, for the wireless 3D NoC. It also illustrates an implementation of a wireless 3D NoC that has on-chip routers and transceivers implemented with a 65 nm process in order to show the feasibility of our proposal. The vertical bubble flow control and conventional VC-based approach on the uni- and bidirectional ring networks are compared with the vertical broadcast bus in terms of throughput, hardware amount, and application performance using a full system multiprocessor simulator. The results show that the proposed bidirectional communication scheme efficiently improves application performance without adding any inductive-coupling transceivers. In addition, the proposed vertical bubble flow network outperforms the conventional VC-based approach by 7.9-12.5 percent with a 33.5 percent smaller router area for building-block SiPs connecting up to eight chips.

Efficient Usage of Transfer based System in Intracity Bus Transit Operation: Sample of Izmir

In this study, intracity bus transit lines based on transfer system are reorganized by using O-D matrix that are obtained from analyzing smart card data. Vertical bus routes that reach the rail system stations are designed and also bus lines that have connection with city center are converted to the regional bus lines. In this way travel times will be decreased thus agency can serve with efficient and reliable bus routes. Decreasing the number of lines and buses that using arterials in the city center can provide more regular headways. Additionally, existing bus line system and transfer based line system are compared and operational benefits (number of vehicles, number of services, total route length, etc.) are examined.

A Die-Selection Method Using Search-Space Conditions for Yield Enhancement in 3D Memory

Three-dimensional (3D) memories using through-silicon vias (TSVs) as vertical buses across memory layers will likely be the first commercial application of 3D integrated circuit technology. The memory dies to stack together in a 3D memory are selected by a die-selection method. The conventional die-selection methods do not result in a highenough yields of 3D memories because 3D memories are typically composed of known-good-dies (KGDs), which are repaired using self-contained redundancies. In 3D memory, redundancy sharing between neighboring vertical memory dies using TSVs is an effective strategy for yield enhancement. With the redundancy sharing strategy, a known-bad-die (KBD) possibly becomes a KGD after bonding. In this paper, we propose a novel dieselection method using KBDs as well as KGDs for yield enhancement in 3D memory. The proposed die-selection method uses three search-space conditions, which can reduce the search space for selecting memory dies to manufacture 3D memories. Simulation results show that the proposed die-selection method can significantly improve the yield of 3D memories in various fault distributions.

A generic readout environment for prototype pixel detectors

Pixel detectors for experimental particle physics research have been implemented with a variety of readout formats and potentially generate massive amounts of data. Examples include the PSI46 device for the Compact Muon Solenoid (CMS) experiment which implements an analog readout, the Fermilab FPIX2.1 device with a digital readout, and the Fermilab Vertically Integrated Pixel device. The Electronic Systems Engineering Department of the Computing Division at the Fermi National Accelerator Laboratory has developed a data acquisition system flexible and powerful enough to meet the various needs of these devices to support laboratory test bench as well as test beam applications. The system is called CAPTAN (Compact And Programmable daTa Acquisition Node) and is characterized by its flexibility, versatility and scalability by virtue of several key architectural features. These include a vertical bus that permits the user to stack multiple boards, a gigabit Ethernet link that permits high speed communications to the system and a core group of boards that provide specific processing and readout capabilities for the system. System software based on distributed computing techniques supports an expandable network of CAPTANs. In this paper, we describe the system architecture and give an overview of its capabilities.

Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks

Three-dimensional chip (3-D) stacking technology provides a new approach to address the so-called memory wall problem. Memory processor chip stacking reduces this memory wall problem, permitting faster clock rates (with suitable processor logic) or permitting multicore access to shared memory using a large number of vertical vias between tiers in the stack, for ultrawide bit path transfer of data and address information to and from various levels of cache. Although a limited amount of parallel access is possible using conventional two-dimensional (2-D) chip memory-processor approaches, 3-D memory-processor stacking greatly extends this to much larger capacity memories. We evaluate high-clock-rate processors as well as shared memory processors with a large number of cores. Various architectural design options to reduce the impact of the memory wall on the processor performance are explored and validated through simulations. Certain architectural features can be implemented in a 3-D chip, such as an ultrawide, ultrashort vertical bus with low parasitic resistance and the elimination of conventional electrostatic discharge, and packaging parasitics required in multiple package 2-D solutions. The objective is to reduce the clocks per instruction figure of merit for high clock speeds in order to deliver significant performance levels. High-clock-rate processors can be designed with SiGe heterostructure bipolar transistors to obtain processors operating on the order of 16 or 32 GHz.

Foveated Dynamic Range of the Pyramidal CMOS Image Sensors

A novel intrascene dynamic range (DR) enhancement technique is proposed for pyramidal CMOS image sensors. The classic CMOS imager 1-D row sampling is replaced by a 2-D ring sampling, the vertical output buses by radial diagonal buses, and the raster scan with a bouncing scan. The result is a foveated DR enhancement mimicking biological vision. Experimental results validate the foveated DR enhancement of more than 50 dB on top of the imager intrinsic DR of 56.6 dB. The 32-ring (64 times 64 pixels) pyramidal CMOS imager is fabricated with dual-voltage (1.8 V, 3.3 V) standard 0.18- CMOS technology.

Compact and power‐saving polysilicon data driver with common‐decoder DA converter (CD‐DAC)

Abstract— A common‐decoder architecture for a data‐driver circuit fabricated by using a polysilicon process has been developed. The architecture achieves a compact circuit and low‐power consumption. In application to an integrated polysilicon data driver for small‐sized displays, this architecture reduces the area of the data driver by removing the vertical bus lines that occupy a large area. It also suppresses the power consumption of the data bus by reducing the number of driven lines in the data bus during word‐to‐word transitions from six to two. By using a conventional 4‐μm design rule, we fabricated an active‐matrix OLED (AMOLED) panel with an integrated six‐bit data‐driver circuit with 384 outputs. The driver circuit had a height of 2.6 mm and a pitch between output lines of 84 μm. The maximum power consumption of the driver was only 5 mW, i.e., 3.8 mW for logic‐data transfer and 1.2 mW for reference‐voltage source. Furthermore, we also fabricated an active‐matrix LCD (AMLCD) panel including driver circuits of the same type as the integrated elements. Six‐bit full‐color images were successfully displayed on both panels.

21.1: Common-Decoder Architecture for Compact and Power-Saving Poly-Si Data-Driver Circuits

We have proposed the common-decoder architecture for a data-driver circuit fabricated by using a poly-Si process: the architecture achieves a compact circuit and low power consumption. In application to a 6-bit data driver, this architecture replaces the 6-bit vertical bus lines that occupy a large area of the conventional DAC with two vertical signal lines. It also suppresses the power consumption of the data bus by reducing the number of bits inverted in word-to-word transitions from six to two. We fabricated an AMOLED panel with an integrated 6-bit data-driver circuit having 384 outputs, using a conventional 4-micron design rule. The driver circuit had a height of 2.6 mm and a pitch between output lines of 84 microns. We confirmed that the driver's maximum power consumption was only 5 mW and that the AMOLED panel showed smooth 64-level gray-scale characteristics. Furthermore, we fabricated an AMLCD panel including driver circuits of the same type as integrated elements. Six-bit full-color images were successfully displayed on both panels.

A TDM-based multibus packet switch

A new packet switch architecture using two sets of time-division multiplexed buses is proposed. The horizontal buses collect packets from the input links, while the vertical buses distribute the packets to the output links. The two sets of buses are connected by a set of switching elements which coordinate the connections between the horizontal buses and the vertical buses so that each vertical bus is connected to only one horizontal bus at a time. The switch has the advantages of: (1) adding input and output links without increasing the bus and I/O adaptor speed; (2) being internally unbuffered; (3) having a very simple control circuit; and (4) having 100% throughput under uniform traffic. A combined analytical-simulation method is used to obtain the packet delay and packet loss probability. Numerical results show that for satisfactory performance, the buses need to run about 30% faster than the input line rate. With this speedup, even at a utilization factor of 0.9, each input adaptor requires only 31 buffers for a packet loss rate of 10/sup -6/. The output queue behaves essentially as an M/D/1 queue.

A VMEbus based data acquisition system for a multi-element detector array

A data acquisition system based on VME standard modules has been designed for MULTICS, a multi-element detector array. The system is composed of a master crate housing CPU's, memories, interface and pattern boards. Up to 15 VME slave crates can be connected using the VMV vertical bus for ADC and TDC boards. A Macintosh Quadra is used as a console to provide a user friendly environment to send commands to the CPU's. Tools in the system include collecting and storing data, displaying histograms, handling all hardware parameters (high and low thresholds, rise time protection etc.). Diagnostic functions and error messages are also available to detect hardware failures or incorrect settings for the modules.

ATF diamagnetic system (abstract)

The diamagnetic diagnostic on ATF consists of two systems. The first uses a single-turn diamagnetic loop in a stainless-steel reentrant tube inside the vacuum vessel. Compensation signals are derived from Rogowski coils mounted on the main helical and vertical coil buses. This arrangement provides maximum sensitivity and the fastest time response, but results in signals which are dominated by noise created by the large ATF SCR power supplies. The nonlinear nature of these supplies, and their coupling, requires the use of hybrid noise reduction processing. The analog compensation loops remove the low-frequency components and digital post-processing removes the high-frequency ones. The second diamagnetic signal is derived from a set of saddle loops which respond directly to the Pfirsch-Schlüter current in the plasma. Typical results are presented. This research was sponsored by the Office of Fusion Energy, U.S. Department of Energy, under contract DE-AC05-84OR21400 with Martin Marietta Energy Systems, Inc.

Line-transfer image sensor operating in the double-reading mode

A solid-state image sensor for 625-line TV cameras has been improved for a novel method of implementation. The sensor's "line-transfer" organization uses conductive buses to transfer photoelectric information in parallel along the vertical direction. The information is then extracted by a CCD output register. A particularly interesting feature of this organization is its ability to separate the useful signal from parasitic signals, such as smearing, through a double reading of the vertical buses. Double reading under good conditions calls for a specific design which will first be described before detailing the double-reading process. The paper then analyzes the bus-reading mechanism and its efficiency, a key parameter for the main electrooptical characteristics. Finally, experimental results are presented and should demonstrate the interest of this sensor organization.