Versatile Place And Route Research Articles

Wire-Length and Run-Time Optimization in FPGA Placement Using Hybrid Iterative Algorithms

This paper introduces hybrid iterative algorithms that combine Particle Swarm Optimization (PSO) and Simulated Annealing (SA) algorithms for Field Programmable Gate Array (FPGA) placement by considering adaptive inertia weight and local minima avoidance. The algorithms target to optimize the wire-length of the nets, run time and critical path delay in the placement of logic blocks. Using the adaptive inertia weight parameter and local minima avoidance, the hybrid PSO-SA algorithm is modified to Time-varying PSO-SA (TPSO-SA) and Modified PSO-SA (MPSO-SA) algorithm, respectively. These different hybrid PSO-SA algorithms are checked for efficiency by comparing with the Versatile Place and Route (VPR) algorithm of the Verilog to Routing (VTR) tool using Microelectronics Centre of North Carolina (MCNC) benchmark circuits. The hybrid PSO-SA algorithms give 5–37% better results for wire-length cost and 20–58% reduction in runtime compared to the VPR placement algorithm on different benchmark circuits. Critical path delay is also taken into consideration.

A Resistive RAM-Based FPGA Architecture Equipped With Efficient Programming Circuitry

Despite the considerable effort has been put on the application of Non-Volatile Memories (NVMs) in Field-Programmable Gate Arrays FPGAs, previously suggested designs are not mature enough to substitute the state of-the-art SRAM-based counterparts mainly due to the inefficient building blocks and/or the overhead of programming structure which can impair their potential benefits. In this paper, we present a Resistive Random Access Memory RRAM-based FPGA architecture employing efficient Switch Box (SB) and Look-Up Table (LUT) designs with programming circuitry integrated in both SB and LUT designs that creates area and power efficient programmable components while precluding performance overhead to these blocks. In addition, we present an efficient scheme to load the configuration bitstream into the memory elements, which makes the configuration time comparable to that of SRAM-based FPGAs. Besides, we investigate the correct functionality and reliability of the programming structure subject to fluctuations in attributes of RRAM cells. Using Versatile Place and Route (VTR) tool with the obtained characteristics of the proposed blocks demonstrate that the average area and delay of the proposed FPGA architecture are 59.4% and 20.1% less than conventional SRAM-based FPGAs. Compared with a recent RRAM-based architecture, the proposed architecture improves the area and power by 49.7% and 33.8% while keeps the delay intact.

Multiple Dice Working as One: CAD Flows and Routing Architectures for Silicon Interposer FPGAs

Large field-programmable gate array (FPGA) systems with multiple dice connected by a silicon interposer are now commercially available. However, many questions remain concerning their key architecture parameters and efficiency, as the signal count between dice is reduced and the delay between the dice is increased compared with a monolithic FPGA. We modify the versatile place and route (VPR) to target interposer-based FPGAs and investigate placement and routing changes and incorporating partitioning into the flow to improve results. Our best computer-aided design (CAD) flow reduces the routing demand for interposer FPGAs with realistic connectivity between dice by 47% and improves the circuit speed by 13% on average. Architecture modifications to add routing flexibility when crossing the interposer are very beneficial and improve routability by a further 11%. With these CAD and architecture enhancements, we find that if an interposer supplies (between dice) 20% of the routing capacity that the normal (within-die) FPGA routing channels supply, there is only a modest impact on circuit routability. Smaller interposer-routing capacities do impact routability; however, minimum channel width increases by 70% when an interposer supplies only 10% of the within-die routing. The interposer also impacts delay, increasing circuit delay by 11% on average for a 1-ns interposer signal delay and a two-die system.

Improvement of cluster-based Mesh FPGA architecture using novel hierarchical interconnect topology and long routing wires

This paper presents an improved interconnect network for Mesh of Clusters (MoC) Field-Programmable Gate Array (FPGA) architecture. Proposed architecture has a depopulated intra-cluster interconnect with flexible Rent's parameter. It presents new multi-levels Switch Box (SB) interconnect which unifies a downward and an upward unidirectional networks based on the Butterfly-Fat-Tree (BFT) topology. To improve the routability of proposed MoC-based FPGA, long routing segments are introduced as a function of channel width with adjustable span. Compared to basic Versatile Place and Route (VPR) Mesh architecture, a saving of 32% of area and 30% of power was achieved with proposed MoC-based architecture. Based on analytical and experimental methods, we identified and explored architecture parameters that control the interconnect flexibility of the proposed MoC-based FPGA such as Rent's parameter, cluster size, Look-Up-Table (LUT) size, long wires span and percentage. Experimental results show that architecture with LUT size 4 and Cluster arity 8 is the best trade-off between power consumption and density. It can also be noted that in general long wires span equal to 4 and percentage between 20% and 30% produce most efficient results in terms of density and power.

Timing slack optimization approach using FPGA hybrid routing strategy of rip-up-retry and pathfinder

To improve the path slack of Field Programmable Gate Array (FPGA), this paper proposes a timing slack optimization approach which utilizes the hybrid routing strategy of rip-up-retry and pathfinder. Firstly, effect of process variations on path slack is analyzed, and by constructing a collocation table of delay model that takes into account the multi-corner process, the complex statistical static timing analysis is successfully translated into a simple classical static timing analysis. Then, based on the hybrid routing strategy of rip-up-retry and pathfinder, by adjusting the critical path which detours a long distance, the critical path delay is reduced and the path slack is optimized. Experimental results show that, using the hybrid routing strategy, the number of paths with negative slack can be optimized (reduced) by 85.8% on average compared with the Versatile Place and Route (VPR) timing-driven routing algorithm, while the run-time is only increased by 15.02% on average.

Reliable Implementation on SRAM-based FPGA using Evolutionary Methods

The mitigation of Single Event Upset (SEU), in the implemented circuits on SRAM-based FPGAs is a crucial issue with increasing usage of such chips in aerospace applications. In this paper, three evolutionary methods have been developed to reduce Soft Error Rate (SER) of such circuits. The first two methods are based on Genetic Algorithm (GA) and Particle Swarm Optimization (PSO), and the other one is a co-evolutionary method which improves the convergence rate and cost of the former methods. The efficiency of these methods has been shown by comparing SER of implemented circuits using these methods with Versatile Place and Route (VPR) counterparts. More than 35% in SER reduction has been achieved for some MCNC benchmark circuits.

Accelerating FPGA Routing Through Parallelization and Engineering Enhancements Special Section on PAR-CAD 2010

We present parallelization and heuristic techniques to reduce the run-time of field-programmable gate array (FPGA) negotiated congestion routing. Two heuristic optimizations provide over 3× speedup versus a sequential baseline. In our parallel approach, sets of design signals are assigned to different processor cores and routed concurrently. Communication between cores is through the message passing interface communications protocol. We propose a geographic partitioning of signals into independent sets to help minimize the communication overhead. Our parallel implementation provides approximately 2.3× speedup using four cores and produces deterministic/repeatable results. When combined, the parallel and heuristic techniques provide over 7× speedup with four cores versus the router in the widely used Versatile Place and Route (VPR) FPGA placement/routing framework, with no significant impact on circuit speed or wirelength.

Cone-based placement for field programmable gate arrays

Deterministic greedy methods have been proposed to place the netlist of configurable logic blocks (CLBs) and primary input output blocks (IOBs) quickly on a two-dimensional (2D) island-style field programmable gate array (FPGA) consisting of either one or multiple 2D island-style arrays of CLBs and IOBs. The first method, ‘ConeCLBPlace’, starts with a random placement of the primary output blocks along the periphery of the 2D array of CLBs, then places the CLBs and primary input blocks in a greedy deterministic way. In the second method, ‘ConeIOBPlace’, the IOBs are first placed on the periphery of the FPGA chip using a deterministic heuristic, and then the CLBs are placed within the 2D array using a typical simulated annealing (SA) flow. The third method, ‘ConePlace’, combines the above two deterministic approaches by first placing the IOBs only using ConeIOBPlace, and then the CLBs using ConeCLBPlace deterministically. Finally, a low-temperature SA is executed in order to obtain a high-quality final placement. ConeCLBPlace and ConePlace produce placements 2.34× and 1.83× faster than the placement step of popular FPGA place-and-route tool VPR (versatile place and route) on the average. The bounding box costs of placement produced by ConeCLBPlace and ConePlace, after execution of the iterative SA steps, are 1.05× and 1.14× of VPR, respectively, on the average, whereas the critical path delay obtained after routing is 1.03× of VPR for both methods on the average, implying almost the same quality of VPR. This justifies the utility of the methods proposed.

FPGA Architecture Optimization Using Geometric Programming

This paper is concerned with the application of geometric programming to the design of homogeneous field programmable gate array (FPGA) architectures. The paper builds on an increasing body of work concerned with modeling reconfigurable architectures, and presents a full area and delay model of an FPGA. We use a geometric programming framework to show how transistor sizing and high-level architecture parameter selection can now be solved as a concurrent optimization problem. We validate the model through the use of simulation program with integrated circuit emphasis (SPICE) models and the versatile place and route (VPR) FPGA architecture simulation tool. Not only does the optimization framework allow architectures to be optimized orders of magnitude faster than previous work, but the combined optimization can lead to different architectural conclusions compared to conventional methods by exploring the coupling between the two sets of optimization variables. Specifically, we show that as delay takes more significance in the objective of the optimization, there should be more lookup tables in a logic block, whereas conventional techniques suggest that there should be fewer lookup tables in an FPGA logic block.

Discrete cooperative particle swarm optimization for FPGA placement

Particle swarm optimization (PSO) is a stochastic optimization technique that has been inspired by the movement of birds. On the other hand, the placement problem in field programmable gate arrays (FPGAs) is crucial to achieve the best performance. Simulated annealing algorithms have been widely used to solve the FPGA placement problem. In this paper, a discrete PSO (DPSO) version is applied to the FPGA placement problem to find the optimum logic blocks and IO pins locations in order to minimize the total wire-length. Moreover, a co-operative version of the DPSO (DCPSO) is also proposed for the FPGA placement problem. The problem is entirely solved in the discrete search space and the proposed implementation is applied to several well-known FPGA benchmarks with different dimensionalities. The results are compared to those obtained by the academic versatile place and route (VPR) placement tool, which is based on simulated annealing. Results show that both the DPSO and DCPSO outperform the VPR tool for small and medium-sized problems, with DCPSO having a slight edge over the DPSO technique. For higher-dimensionality problems, the algorithms proposed provide very close results to those achieved by VPR.

Hierarchical FPGA placement

Field-programmable gate arrays (FPGAs) are semiconductor chips that can realize most digital circuits on site by specifying programmable logic and their interconnections. The use of FPGAs has grown almost exponentially because they dramatically reduce design turnaround time and startup cost for electronic products compared with traditional application-specific integrated circuits (ASICs). Efficient computer-aided-design tools are required to compile hardware descriptions into bitstream files that are used to configure the target FPGA to implement the desired circuits. Currently, the compile time, which is dominated by placement and routing time, can easily be hours or even days for large (8-million-gate) FPGAs. With 40-million-gate FPGAs on the horizon, these prohibitively long compile times may nullify the time-to-market advantage of FPGAs. This paper presents two novel placement heuristics that significantly reduce the computation time required to achieve high-quality placements, compared with the versatile place and route (VPR) tool. The first algorithm is an enhancement of simulated annealing (SA) that attempts to solve the placement problem top-down by considering all modules at the flat level. The second algorithm involves a hierarchical approach based on a two-step procedure that first proceeds bottom-up (grouping highly connected modules together) and then top-down (declustering). The overall effect is to reduce the number of entities needing to be considered at each level, such that time-consuming methods like SA become feasible for very large problems. Experimental results show a 70?80% reduction in runtime, coupled with very high-quality placements.

RBI: Simultaneous Placement and Routing Optimization Technique

The main goal of this paper is to develop deeper insights into viable placement-level optimization of routing. Two primary contributions are made. First, an experimental framework in which the viability of predictive or probabilistic models of routing congestion for optimization during detailed placement can be evaluated is developed. The main criterion of consideration in these experiments is how (un)reliably various models from the literature detect routing hot spots. It was concluded that such models appear to be too unreliable for detailed placement optimization. Second, motivated by the first result, a single combinatorial framework in which cell placement and exact routing structures are captured and optimized is presented; the framework relies on the trunk decomposition of global routing structures, and optimization is performed by generalization of the optimal interleaving algorithm. An implementation of this framework is studied in the field-programmable gate array domain. The technique can reduce the number of channels at maximum density by more than 60% on average with maximum reduction of more than 81% for optimized global routing taking only 75% of the Versatile Place and Route (VPR) placement and routing runtime combined. For the standard cell domain, routing-based interleaving, on average, reduces the maximum track count by more than two tracks with a maximum reduction of nine tracks

An Approach to Placement-Coupled Logic Replication

This paper presents a set of techniques for placement-coupled timing-driven logic replication. Two components are at the core of the approach. First, is an algorithm for optimal timing-driven fanin tree embedding; the algorithm is very general in that it can easily incorporate complex objective functions (e.g., placement costs) and can perform embedding on any graph-based target. Second, the replication tree is introduced, which allows to induce large fanin trees from a given circuit, which can then be optimized by the embedder. The authors have built an optimization engine around these two ideas and report promising results for the field-programmable gate array (FPGA) domain including clock period reductions of up to 36% compared with a timing-driven placement from versatile place and route (VPR) (Marquardt , 2000) and almost double the average improvement of local replication (Beraudo and Lillis, 2003). These results are achieved with modest area and runtime overhead. In addition, issues that arise due to reconvergence in the circuit specification are addressed. The authors build on the replication tree idea and enhance the timing-driven fanin tree embedding algorithm to optimize subcritical paths, yielding even better delay improvements.

FPGA placement optimization by two-step unified Genetic Algorithm and Simulated Annealing algorithm

Genetic Algorithm (GA) is a biologically inspired technique and widely used to solve numerous combinational optimization problems. It works on a population of individuals, not just one single solution. As a result, it avoids converging to the local optimum. However, it takes too much CPU time in the late process of GA. On the other hand, in the late process Simulated Annealing (SA) converges faster than GA but it is easily trapped to local optimum. In this letter, a useful method that unifies GA and SA is introduced, which utilizes the advantage of the global search ability of GA and fast convergence of SA. The experimental results show that the proposed algorithm outperforms GA in terms of CPU time without degradation of performance. It also achieves highly comparable placement cost compared to the state-of-the-art results obtained by Versatile Place and Route (VPR) Tool.

A detailed power model for field-programmable gate arrays

Power has become a critical issue for field-programmable gate array (FPGA) vendors. Understanding the power dissipation within FPGAs is the first step in developing power-efficient architectures and computer-aided design (CAD) tools for FPGAs. This article describes a detailed and flexible power model which has been integrated in the widely used Versatile Place and Route (VPR) CAD tool. This power model estimates the dynamic, short-circuit, and leakage power consumed by FPGAs. It is the first flexible power model developed to evaluate architectural tradeoffs and the efficiency of power-aware CAD tools for a variety of FPGA architectures, and is freely available for noncommercial use. The model is flexible, in that it can estimate the power for a wide variety of FPGA architectures, and it is fast, in that it does not require extensive simulation, meaning it can be used to explore a large architectural space. We show how the model can be used to investigate the impact of various architectural parameters on the energy consumed by the FPGA, focusing on the segment length, switch block topology, lookuptable size, and cluster size.