Verification Of Digital Systems Research Articles

Predicting Formal Verification Resource Needs (Computation Time and Memory) through Machine Learning

This paper presents an application of Machine Learning (ML) for estimating the resource requirements (time and memory) for formal verification of digital systems. Formal Verification has become the main bottleneck in the digital design process. As designs grow in size, the verification cost exponentially increases. Some verification efforts fail when the cost of the verification is too large. The most common failures are due to state explosion problem when memory runs out or when verification does not meet time constraints and cannot complete within the given time. For this reason, having an estimation of the computation resources beforehand can be valuable. In this work, a neural network is used to predict the formal verification cost for a diverse collection of designs. Experiments with a large variety of Verilog benchmarks have been conducted. In each experiment, the specific features of a given design are extracted, the design is synthesized and formally verified, and the verification time and memory usage are recorded. The neural network then uses this data to learn the correlation between design features and verification cost. A genetic algorithm experimented with different neural network designs to determine an appropriate framework. The experimental results confirm that the developed neural network can predict the resource requirements and memory usage with reasonable accuracy.

An Automatic Functional Coverage for Digital Systems Through a Binary Particle Swarm Optimization Algorithm with a Reinitialization Mechanism

At present, functional verification represents the most expensive part of the digital systems design. Moreover, different problems such as: clock synchronization, code compatibility, simulation automation, new design methodologies, proper use of coverage metrics, among others represent challenges in this area. The automated test vector generation is involved in these problems. In this work, an automated functional test sequences generation for digital systems based on the use of coverage models and a binary Particle Swarm Optimization algorithm with a reinitialization mechanism (BPSOr) is described. Also, a comparison with other meta-heuristic algorithms such as: Genetic algorithms (GA) and pseudo-random generation is presented using different fitness functions, coverage models and devices under verification. The main strategy is based on the combination of the simulation and meta-heuristic algorithms to test the device behavior through the generation of test vector sequences. According to the results, the proposed test generation method represents a good alternative to increase the functional coverage during the automated functional verification of block-level digital systems verification.

CYBERSPACE DEVELOPMENT AND INFORMATION SECURITY

Aim of this article is significant improving the quality of services delivered by the software, hardware, and cyberspace networks, as well as reducing the operation cost through the creation of infrastructures IP, providing user-friendly operation, testing and removal of non-functional destructive components. A model of evolving cyberspace is proposed, where the subjects are interacting processes or phenomena with physical carrier in the form of computer systems and networks. The universal nonarithmetic model for structural estimating the relation of two objects in cyberspace is developed. It is designed for recognition the set-theoretic or vector interaction of objects. The architecture of multimatrix processor is created, focused on increasing the performance of embedded functional failure diagnosis in software or hardware. Infrastructures IP for protecting software against malicious code and verification of digital systems are described. The structural model for recognizing the destructive patterns based on the relationships of the input pattern, standards and similarity criteria.

FPGA-Based In-Circuit Verification of Digital Systems

In general hardware designers design integrated circuit with hardware description languages or schematic diagram. However the growth of circuit complexity makes circuit design error prone and time consuming. The resulting descriptions tend to be lengthy and hard to reason about. Therefore functional simulation, timing simulation and in-circuit test are three essential steps to ensure that the designed circuit is correct. This paper presents a method of in-circuit verification on FPGA using UART communication between the computer and the FPGA board. Through UART, designers can convert the parallel input vector into a set of serial stimulus signals and send them to the FPGA board, and also can receive the feedback serial signals from the FPGA board and reconvert them into a parallel output vector. Given the input and output ports of the verified circuit component, a verification platform based on UART communication will be customized automatically by the in-circuit verification platform generator. This breaks the constraint of the FPGA board's limited pins and supports wide-scale input/output vectors and can be applied in in-circuit test of digital circuit.

Cultural algorithm for minimization of binary decision diagram and its application in crosstalk fault detection

The binary decision diagrams (BDDs) can give canonical representation to Boolean functions; they have wide applications in the design and verification of digital systems. A new method based on cultural algorithms for minimizing the size of BDDs is presented in this paper. First of all, the coding of an individual representing a BDDs is given, and the fitness of an individual is defined. The population is built by a set of the individuals. Second, the implementations based on cultural algorithms for the minimization of BDDs, i.e., the designs of belief space and population space, and the designs of acceptance function and influence function, are given in detail. Third, the fault detection approaches using BDDs for digital circuits are studied. A new method for the detection of crosstalk faults by using BDDs is presented. Experimental results on a number of digital circuits show that the BDDs with small number of nodes can be obtained by the method proposed in this paper, and all test vectors of a fault in digital circuits can also be produced.

Digital System Verification: A Combined Formal Methods and Simulation Framework

Integrated circuit capacity follows Moore's law, and chips are commonly produced at the time of this writing with over 70 million gates per device. Ensuring correct functional behavior of such large designs before fabrication poses an extremely challenging problem. Formal verification validates the correctness of the implementation of a design with respect to its specification through mathematical proof techniques. Formal techniques have been emerging as commercialized EDA tools in the past decade. Simulation remains a predominantly used tool to validate a design in industry. After more than 50 years of development, simulation methods have reached a degree of maturity, however, new advances continue to be developed in the area. A simulation approach for functional verification can theoretically validate all possible behaviors of a design but requires excessive computational resources. Rapidly evolving markets demand short design cycles while the increasing complexity of a design causes simulation approaches to provide less and less coverage. Formal verification is an attractive alternative since 100% coverage can be achieved; however, large designs impose unrealistic computational requirements. Combining formal verification and simulation into a single integrated circuit validation framework is an attractive alternative. This book focuses on an Integrated Design Validation (IDV) system that provides a framework for design validation and takes advantage of current technology in the areas of simulation and formal verification resulting in a practical validation engine with reasonable runtime. After surveying the basic principles of formal verification and simulation, this book describes the IDV approach to integrated circuit functional validation. Table of Contents: Introduction / Formal Methods Background / Simulation Approaches / Integrated Design Validation System / Conclusion and Summary

FPGAを用いたディジタルシステム検証とシステムの実現

FPGAを用いたディジタルシステム検証とシステムの実現

Canonical representations of high-level decision diagrams

In this paper we give a short overview of the decision diagrams, and define a special class of high-level decision diagrams (HLDD) for formal representation of digital systems. We show how the HLDDs can be used for high-level verification of digital systems. For this purpose, HLDDs are represented by characteristic polynomials as a canonical form of HLDDs. The polynomials can be used for proving the equivalence between two HLDDs, which have the same functionalities but may have different internal structures. Some possibilities are shown how to cope with the complexity of the verification problem.

Word-level symbolic simulation in processor verification

Formal verification of RT-level digital systems has attracted attention due to its efficiency over traditional simulation methods. This technology is still at its infancy and faces problems of property checking efficiency, memory explosion, and simultaneously the handling of data and control modules of hardware to be verified. Various methods of representing hardware and/or algorithms for property checking have been proposed to overcome these problems. One such method is symbolic simulation, which is attracting increasing interest in the area of digital circuit validation. It allows the verification engineer to explore all, or a major portion, of the circuit's state space without the need for designing time-consuming test stimuli. However, the complexity and unpredictable run-time behaviour of symbolic simulation have limited its scope to small-to-medium size circuits. A proposed solution for formal verification of digital systems is the use of symbolic simulation of a word-level representation. For this purpose a high-level model is described for digital circuits in the form of a distributed table-based representation that is suitable for application of formal verification property checking. The distributed table-based representation means that the next-state, output and intermediate signals are represented in a table that retains hierarchy of signal assignments without flattening them. In the model a design is represented by an hierarchical structure of integer equations, instead of a binary decision diagram. A subset of PSL (property specification language) can be directly applied to circuits described in the proposed representation. In addition, a set of integer equations are symbolically simulated based on the specified property in a predictable time. The word-level representation is a canonical form of the linear Taylor expansion diagram.

Requirements specification and analysis of digital systems using fuzzy and marked Petri nets

Fuzzy information often appears in the system requirements. Fuzzy Petri nets (FPN) are Petri nets in which certain fuzzy truth values are assigned to its transitions. We show how the FPN model can be used for formal specification and verification of digital systems. The consistent FPN model is actually a state machine, from which we can obtain a consistent marked Petri net (MPN) model. Based on the consistent MPN model, the hardware prototype at register transfer level can be easily induced by using the optimization rules. Finally, main results are presented in the form of three theorems and are supported by some experiments.

Formal verification of digital systems by automatic reduction of data paths

Verification of properties (tasks) on a system P containing data paths may require too many resources (memory space and/or computation time) because such systems have very large and deep state spaces. As pointed out by Kurshan, what is needed is a reduced system P' which behaves exactly as P with respect to the properties that must be proved, but more compact than P, so that the verification can be easily performed. The process of finding P' from P is called reduction. P is specified by a network of interacting finite-state machines for data paths and controllers, and tasks are specified by finite-state automate. The verification of a task T on P is performed by the language containment check L(P)/spl sube/L(T), where L(P) is the language generated by P and L(T) is the language accepted by T. It has been shown that, under appropriate conditions, the system P can be reduced to P' and the task T to T' such that L(P')/spl sube/L(T')/spl hArr/L(P)/spl sube/L(T). The direct language containment check L(P)/spl sube/L(T) is no longer needed; it is replaced by L(P')/spl sube/L(T'), which is less expensive. More specifically, for the purpose of simplifying the verification of some properties, the system implementation is abstracted locally with respect to the behavior under observation (i.e., bottom-up reduction), in the context of an integrated top-down design/verification technique. The tasks that one may want to verify can express both safety and fairness constraints. In this paper, we prove that the reduction of some data paths to four-state, nondeterministic finite-state machines, and the redundancy removal performed on the controllers is a homomorphic transformation, so that the simplified language containment check can automatically be applied without testing the validity of the homomorphism. This homomorphism correctness verification, required when a formal proof is not available, can be executed using a tool like Cospan, but it may not be completed when the state space to be traversed is too large and deep. The redundancy removal performed on the controllers is important because it eliminates the spurious behaviors introduced in the system by the nondeterminism of the reduced data paths. Redundancy, in fact, may induce a failure in the verification of L(P')/spl sube/L(T'), while L(P)/spl sube/L(T) actually holds. In order to show the effectiveness of the proposed methodology, we verify properties on an extended version of the Mead-Conway Traffic Light Controller, on a modified IRQ communication protocol, and on a relatively prime integers checker and generator.

Incremental Methods for FSM Traversal

Computing the set of reachable states of a finite state machine, is an important component of many problems in the synthesis, and formal verification of digital systems. Computing the reachable states is computationally expensive due to the explosion in the number of states in real designs. However, the process of design is usually iterative, and the designer may modify and recompute information many times. Unfortunately, the reachability computation is called each time the designer modifies the system, because current methods for reachability analysis are not incremental. The representation of the reachable states that is currently used [1] in synthesis and verification, is inherently non-updatable; in addition it tends to have a large representation, even when the finite state machine itself has a compact representation. We solve all these problems by presenting alternate ways to represent the reachable set, and incremental algorithms that can update the new representation each time the designer changes the system. The incremental algorithms use the reachable set computed at a previous iteration, and information about the changes to the system to update it, rather than compute the reachable set from the beginning. This results in considerable savings in time, as demonstrated by the results

Formal specification and verification of digital systems

Formal specification and verification of digital systems

Design verification of digital systems based on logic programming

It has already been shown how Prolog can be used as a hardware description language. Prolog enables the use of the hierarchical structure of a design by breaking the design into pieces and using the verification strategy recursively. Moreover, Prolog enables a dynamic updating of a database such that the correctness of each type of module is proved exactly once and recorded, so that use can be made of them later in the verification process. Thus, the complexity of the verification process is proportional to the number of different types of modules and not to the number of primitive components. In short, the use of Prolog offers a rare combination of convenient hardware description tools, applications of software techniques in hardware manipulations, and the application of AI concepts. Further major considerations, not treated until now, are presented in this paper. A design verification program named SYMEX, which is based on symbolic execution, is treated in detail, demonstrating how Prolog deals with the following fundamental issues: (a) An inductive proof of a module with N inputs; (b) A natural treatment of input and output sequences having an undefined length; (c) Information transfer in and out of a design; (d) A structural analysis of a module.

Specification and verification of digital systems using higher-order predicate logic

Specification and verification of digital systems using higher-order predicate logic