Verification Of Digital Circuits Research Articles

Formal timing analysis of gate-level digital circuits using model checking

Due to the continuous reduction in the transistors sizing ruled by the Moore’s law, digital devices have become smaller, and more complex resulting in an enormous rise in the delay variations. Therefore, there is a dire need of precise and rigorous timing analysis to overcome anomalies during the timing analysis. Timings of digital circuits can be verified using various simulation or static timing analysis (STA) based tools but they provide estimated results due to their inherent in-exhaustive nature or report timing paths corresponding to non-existent functional paths, respectively. Formal verification provides complete and sound analysis results and has widely been used for the functional verification of digital circuits but its application in the timing analysis domain is somewhat limited. We present a generic framework to perform formal timing analysis of digital circuits with the help of Uppaal model-checker. The given digital circuit along with its timing parameters in the form of state transition diagram are modeled using timed automata in the Uppaal model checker. Timing delays are calculated from corresponding technology parameters, and Quartus Prime Pro is used to obtain the information about the circuits’ paths. In order to make the analysis scalable, we also propose a novel path partitioning technique and compare its results with complete path analysis and traditional STA. The formal model is verified with the help of properties to assess the timing characteristics, like time period of a clock, critical path, and propagation delay of the considered circuit. Modeling and verification of ISCAS-85 and ISCAS-89 benchmark circuits is presented for illustration purposes.

HVoC: a Hybrid Model Checking - Interactive Theorem Proving Approach for Functional Verification of Digital Circuits

HVoC: a Hybrid Model Checking - Interactive Theorem Proving Approach for Functional Verification of Digital Circuits

Adaptive random testing with total cartesian distance for black box circuit under test

<p>Testing and verification of digital circuits is of vital importance in electronics industry. Moreover, key designs require preservation of their intellectual property that might restrict access to the internal structure of circuit under test. Random testing is a classical solution to black box testing as it generates test patterns without using the structural implementation of the circuit under test. However, random testing ignores the importance of previously applied test patterns while generating subsequent test patterns. An improvement to random testing is Antirandom that diversifies every subsequent test pattern in the test sequence. Whereas, computational intensive process of distance calculation restricts its scalability for large input circuit under test. Fixed sized candidate set adaptive random testing uses predetermined number of patterns for distance calculations to avoid computational complexity. A combination of max-min distance with previously executed patterns is carried out for each test pattern candidate. However, the reduction in computational complexity reduces the effectiveness of test set in terms of fault coverage. This paper uses a total cartesian distance based approach on fixed sized candidate set to enhance diversity in test sequence. The proposed approach has a two way effect on the test pattern generation as it lowers the computational intensity along with enhancement in the fault coverage. Fault simulation results on ISCAS’85 and ISCAS’89 benchmark circuits show that fault coverage of the proposed method increases up to 20.22% compared to previous method.</p>

Formal Verification of Digital Circuits Using Simulator with Mathematical Foundation

To ease hardware design process, circuits are normally designed in description languages such as Verilog and VHDL. The correctness of circuits is normally checked by exhaustive simulation in simulators such as Icarus and VCS. Both the description languages Verilog/VHDL and simulators Icarus/VCS do not have mathematical foundations and hence are not reliable and cannot be used to mathematically prove correctness of circuit designs. Hardware description languages with mathematical (formal) foundation such as VeriFormal, on the other hand, are more reliable, trustworthy and can be used for robust design. In this paper, we report our results of formal verifications of two simple hardware circuits designed in the formal description language VeriFormal. Using the VeriFormal simulator and the accompanied type checker tools, we prove reliability properties type safety, functional correctness and functional equivalence of the digital circuits.

Parallelization of Cycle-Based Logic Simulation

Verification of digital circuits by Cycle-based simulation can be performed in parallel. The parallel implementation requires two phases: the compilation phase, that sets up the data needed for the execution of the simulation, and the simulation phase, that consists in executing the parallel simulation of the considered circuit for a certain number of cycles. During the early phase of design, compilation phase has to be repeated each time a bug is found. Thus, if the time of the compilation phase is too high, the advantages stemming from the parallel approach may be lost. In this work we propose an effective version of the compilation phase and compute the corresponding execution time. We also analyze the percentage of execution time required by the different steps of the compilation phase for a set of literature benchmarks. Further, we implemented the simulation phase exploiting the GPU architecture, and we computed the execution times for a set of benchmarks obtaining values comparable with literature ones. Finally, we implemented the sequential version of the Cycle-based simulation in such a way that the execution time is optimized. We used the sequential values to compute the speedup of the parallel version for the considered set of benchmarks.

Investigation of Correlation of Test Sequences for Reliability Testing of Digital Physical System Components

The topical problem of effective verification of digital circuits of different physical systems remains a hot topic. Devices ranging from embedded components to perform specific tasks or experiments to modern communication clusters used for data transmission are concerned. The method of synthesis of the test sequences is based on injection of faults into a reference circuit and deriving a corresponding distinguishing sequence which detects this fault. The method is known as mutation testing and is widely used for the synthesis of high-quality verification tests for digital circuits. Naturally, test suits that detect faults of various classes, and larger amount of faults, are of greater interest. The paper studies the correlation between different test suits derived for different mutant types. The considered fault types include 1) single stuck-at faults, 2) bridges, and 3) hardly detectable faults, i.e., slightly modifying the behavior of a single circuit gate. Tests for detecting faults of each type are derived for the B01-B10 benchmark package (ITC’99 benchmarks (Second Release)), which are components of physical systems intended for various applications including processing of data obtained, load balancing systems, etc. Experiments aim to access the fault coverage of the test derived for one mutant type against faults of other types. It is shown experimentally that the synthesis of tests of one type, including a single stuck-at fault test, is insufficient, because its fault coverage for faults of other types cannot exceed 60%.

Modeling and simulation of circuits with shared structurally synthesized BDDs

Modeling and simulation are critical tools for the analysis of testability and verification of digital circuits. BDDs are a well-known model for manipulating Boolean functions. However, the traditional BDDs mainly address modeling the function of the digital circuits, and not the structural aspects that are important for testability analysis. We propose a new type of BDD in the form of Shared Structurally Synthesized BDD (S3BDD) for representing the structure and simulating the faults in digital circuits. The paper presents a method for synthesis of S3BDDs, offers a formula for calculating the minimal size of the model, and proposes a method for parallel pattern simulation with S3BDDs We demonstrate a considerable increase in the speed-up of simulation of digital circuits using S3BDDs.

Determining Equivalent Signal Lines by Weight Value Assignment for Logic Verification of Digital Circuits

The VLSI technology has led to the increased complexity in hardward design, therefore the verification for the correctness of circuit operations has become an exrtremely important task. The verification procedure can be reduced by means of the equivalent signal lines in the circuits. In this paper, a new method is presented for determining the equivalent signal lines, the method utilizes the weight value assignment of signal lines in circuits. First of all, the method makes use of the topological information of circuits to perform forward weight value assignments, assign weight values to the signal lines from the primary inputs to primary outputs. Afterwards, carry out the backward weight value assignment, assign weight values to the signal lines from the primary outputs to primary inputs. Secondly, carry out the random pattern simulation to further check the equivalence of signal lines. A lot of experimental results show that the verification of digital circuits can be carried out effectively by using the method proposed in this paper, the time being needed for the verification procedure can be cut down by utilizing the equivalent signal lines.

New developments in the theory of Gröbner bases and applications to formal verification

We present foundational work on standard bases over rings and on Boolean Gröbner bases in the framework of Boolean functions. The research was motivated by our collaboration with electrical engineers and computer scientists on problems arising from formal verification of digital circuits. In fact, algebraic modelling of formal verification problems is developed on the word-level as well as on the bit-level. The word-level model leads to Gröbner basis in the polynomial ring over Z / 2 n while the bit-level model leads to Boolean Gröbner bases. In addition to the theoretical foundations of both approaches, the algorithms have been implemented. Using these implementations we show that special data structures and the exploitation of symmetries make Gröbner bases competitive to state-of-the-art tools from formal verification but having the advantage of being systematic and more flexible.

Analog Circuit Verification: a State of an Art

Extending formal verification methodology toward analog circuits is a very challenging task that will occupy researchers for some time. To put this challenge in context we sketch some of the history of digital circuit verification as well as more recent attempts to adapt it to continnuous and hybrid systems.

Application of symbolic FSM Markovian analysis to protocol verification

Computer-aided design tools for Markovian analysis and verification of digital circuits have gained much interest in the last few years. This is mainly due to the advent of effective data structures, e.g., binary and algebraic decision diagrams, for Boolean and pseudo-Boolean function representation and manipulation. The authors illustrate how those tools can be successfully exploited to analyse the behavior and verify the correctness of a communication protocol. They first consider the case of single protocol entities running in isolation, and present a simple application example (i.e. the sender entity of the alternating bit protocol). Then, informally illustrate how the analysis approach can be extended to the general case of multi-layer protocol stacks and complete communication systems.

Ordered binary decision diagrams and minimal trellises

Ordered binary decision diagrams (OBDDs) are graph-based data structures for representing Boolean functions. They have found widespread use in computer-aided design and in formal verification of digital circuits. Minimal trellises are graphical representations of error-correcting codes that play a prominent role in coding theory. This paper establishes a close connection between these two graphical models, as follows. Let /spl Cscr/ be a binary code of length n, and let f/sub c/(x/sub 1/, ..., x/sub n/) be the Boolean function that takes the value 0 at x/sub 1/, ..., x/sub n/ if and only if (x/sub 1/, ..., x/sub n/)/spl isin//spl Cscr/. Given this natural one-to-one correspondence between Boolean functions and binary codes, we prove that the minimal proper trellis for a code /spl Cscr/ with minimum distance d>1 is isomorphic to the single-terminal OBDD for its Boolean indicator function f/sub c/(x/sub 1/, ..., x/sub n/). Prior to this result, the extensive research during the past decade on binary decision diagrams (in computer engineering) and on minimal trellises (in coding theory) has been carried out independently. As outlined in this work, the realization that binary decision diagrams and minimal trellises are essentially the same data structure opens up a range of promising possibilities for transfer of ideas between these disciplines.

On the formal specification and verification of digital circuits

This paper presents a design technique for digital circuits at register-transfer level (RTL). The two most important notions within the design trajectory are the formal specification of the circuit and the formal verification of an implementation, that a designer comes up with, against this specification. A mathematical description formalism is presented that can be used to describe both the specification and the implementation of RTL circuits and, furthermore, to formally verify the implementation against the specification. As an example, the design of an n-th order infinite impulse response (IIR) filter is presented. It is shown that several different implementations are possible and that the trade-off between speed and chip area can be made very precisely.

A general purpose accelerator for digital system design

With the growing acceptance of simulation tools for the analysis and verification of digital circuits, and the ever increasing complexity of digital system designs involving multiple ASICs and complex commercial VLSI components, designers are demanding increased performance from the design tools. This paper outlines the problems associated with accelerating design verification tools focused for system-level design. The architecture of a commercially available general purpose hardware accelerator is then described to see how these problems can be addressed.