Vedic Multiplication Technique Research Articles

Comparative study of single precision floating point division using different computational algorithms

<span>This paper presents different computational algorithms to implement single precision floating point division on field programmable gate arrays (FPGA). Fast division computation algorithms can apply to all division cases by which an efficient result will be obtained in terms of delay time and power consumption. 24-bit Vedic multiplication (Urdhva-Triyakbhyam-sutra) technique enhances the computational speed of the mantissa module and this module is used to design a 32-bit floating point multiplier which is the crucial feature of this proposed design, which yields a higher computational speed and reduced delay time. The proposed design of floating-point divider using fast computational algorithms synthesized using Verilog hardware description language has a 32-bit floating point multiplier module unit and a 32-bit floating point subtractor module unit. Xilinx Spartan 6 SP605 evaluation platform is used to verify this proposed design on FPGA. Synthesis results provide the device utilization and propagation delay parameters for the proposed design and a comparative study is done with previous work. Input to the divider is provided in IEEE 754 32-bit formats.</span>

Modified Binary Vedic Multiplication Using Carry Save Adder

This paper presents modified binary Vedic multiplication using carry save adder. The suggested modified binary Vedic multiplication technique is more efficient in terms of delay. The proposed circuit is implemented in Verilog HDL. The Xilinx ISE Design Suite 14.6 is used for circuit synthesis. The simulation done for 4-bit ,8-bit 16-bit multiplication operations. In this paper, the simulation waveforms are shown only for 4-bit and 8-bit multiplication operation based on the modified Vedic multiplication technique using carry save adder. The vedic multiplication method can be extended for a larger bit size. The delay compared with normal multiplication technique.

Implementation of high precision/low latency FP divider using Urdhva–Tiryakbhyam multiplier for SoC applications

The increasing demand of Industrial and Scientific data intensive applications are higher precision arithmetic with reduced computation time. In this paper, we designed a high-precision, fully pipelined 32-bit floating-point (FP) divider using Newton–Raphson (NR) algorithm realized with Urdhva–Tiryakbhyam (UT) multiplier for System on Chip applications. The divider design is based on Newton–Raphson (multiplicative) method and it supports all IEEE rounding modes with a latency of 15 cycles. The iterative NR computations are performed by using FP multiplier and FP adder. The key module of FP multiplier for calculating mantissa part is UT multiplier. It’s an ancient Vedic multiplication technique used from few centuries back for doing fast multiplications. We implemented two UT multipliers: one using carry look-ahead adders and another one using carry save adders. The results show that, the proposed architectures have 12% better precision with 24% high throughput than existing algorithms, at the cost of high on-chip power. The inputs to the divider are represented in IEEE-754 standard. The design uses Xilinx Vivado software and it is implemented on Virtex7 FPGA.

Delay Efficient Vedic Multiplier for DSP

Multipliers are very essential blocks in any arithmetic and logic unit, accumulators and Digital signal processors. Due to the enlarging check on delay, design of faster multipliers is desired. Amidst numerous multipliers, Vedic multipliers are favored for their speed of operation. There are sixteen sutras in Vedic mathematics out of which four are multiplication techniques. “URDHVA TIRYAKBHYAM” is the most efficient vedic multiplication technique in terms of speed. In this paper we aim to develop a multiplier using Ripple Carry Adder and parallel prefix adders which carry out the “URDHVA TIRYAKBHYAM” sutra with improved speed of operation by providing the minimum delay for the multiplication of numbers regardless of their bit sizes. A vast majority of the engineering domain consists of ubiquitous technologies like DSP. As it is one of the most rapid growing technologies of the 21st Century, it faces challenges and improvisation at each step. Engineers are working diligently to improve the quality of Digital Signal processors and major breakthroughs are being made at a very good rate. Proposed multiplier could be applied for such DSP applications. Verilog language has been used for the coding. Xilinx Vivado Tool is used for synthesis and Model Sim 5.4 has been used for simulation.

Design and Synthesis of Single Precision Floating Point Division based on Newton-Raphson Algorithm on FPGA

This paper describes a single precision floating point division based on Newton-Raphson computational division algorithm. The Newton-Raphson computational algorithm is implemented using 32-bit floating point multi-plier and subtractor. The salient feature of this proposed design is that the module for computing mantissa in 32-floating point multiplier is designed using a 24-bit Vedic multiplication (Urdhva-triyakbhyam-sutra) technique. 32-bit floating point multiplier, designed using Vedic multiplication technique, yields a higher computational speed, hence, is efficiently used in floating point divider. Another important feature is the efficient use of device utilization parame-ters and reduced power consumption. An advantage of the Newton-Raphson algorithm is the higher versatility and precision. For representing 32-bit floating point numbers, IEEE 754 standard format is used. ISim simulator is used for simulation. The proposed floating point divider is designed using Verilog Hardware Description Language (HDL) and is verified on Xilinx Spartan 6 SP605 Evaluation Platform FPGA.

An Efficient Multi-Precision Floating Point Adder and Multiplier

Background: Floating Point (FP) computation is an indispensible task in various applications. The floating point additions and multiplications are core operations in complex multiplication, in which inputs should be given in IEEE 754 standard formats. Methods: The proposed design performs one double precision, or two single precision addition and multiplication operations in parallel, have been designed efficiently using resource sharing for both precision operands with minimal multiplexing circuitry. The proposed floating point multiplier makes use of Vedic multiplication algorithm, because in array multiplication sharing of multiplication is not possible. Findings: The proposed architecture has been synthesized using 0.18µm standard cell library. Compared to previous architectures the proposed DPdSP architecture has 20% reduced power and 5% area reduction. Conclusion: The DPdSP adder and multiplier consume less power than the conventional adder. Using Vedic multiplication technique shows a minimum power compared with all other type of architecture.