Vector-sum Phase Shifter Research Articles

A Self-Body-Biasing Network of Vector Sum Phase Shifter for Reduction of Output Capacitance Variation and Supply Current Variation

A Self-Body-Biasing Network of Vector Sum Phase Shifter for Reduction of Output Capacitance Variation and Supply Current Variation

An integrated LNA‐phase shifter in 65 nm CMOS for Ka‐band phased‐array receivers

SummaryIn this paper, a vector‐sum phase shifter (VSPS) integrated with a wideband high‐gain low‐noise amplifier (LNA) for Ka‐band phased‐array receivers is presented. The digitally controlled VSPS based on the RF phase shifting architecture consists of a modified I/Q signal generator with additional inductor resonance and a programmable variable gain amplifier (VGA) based on Four 3 × 4 transistor arrays. Besides the reduced parasitic effect of the I/Q signal generator, an Equidistant Contraction Technology (ECT) is used in the VGA, to maintain higher phase shift accuracy of the VSPS. A multistage LNA with series inductor peaking is adopted to fulfill the flat wideband gain, where LC resonance networks are used as interstage matching to compensate for gain roll‐off at a higher frequency. Based on simulations in 65 nm CMOS technology, the presented LNA‐Phase shifter has achieved an average NF of 3.24–3.66 dB, and an average gain of 13.1–23.6 dB. Moreover, an RMS phase error of 1.1–12.6°, an RMS gain error of 4.2–5.6 dB, and an RMS magnitude error of 2.1–2.8 dB are maintained across 27–40 GHz, with a 360° phase shift coverage in steps of approximately 2.8125°. The chip consumes 16.83 mW from a 1.2 V supply voltage, and the occupied area is 0.65 mm2.

A ku-band common-leg transceiver with built-in configurable register in 130-nm CMOS technology for phased-array systems

To solve the bottleneck of amplitude and phase accuracy deterioration caused by process and unpredictable errors, this paper proposes a Ku-band common-leg transceiver with built-in configurable register to achieve 64-state amplitude and phase accuracy correction, respectively, by redefining control codes of each state after taping out. Two-stage cascaded variable gain amplifiers (VGAs) and the vector-summing phase shifter (VSPS) with tail current source controlled by DAC are adopted to achieve large amplitude and phase coverage of 31.5 dB with the LSB of 0.5 dB and 360° with the LSB of 5.625°, respectively. According to the measurement results, in the frequency range of 14–18 GHz, the chip has amplitude accuracy with the root mean square (rms) error of ＜ 0.4 dB, while the rms phase error is ＜ 5.3°. The phase shifting accuracy is measured to be ＜ 2.2°, while the rms amplitude error is ＜ 0.67 dB. The receiving and transmitting channels have reference gain of 3.6–6 dB and 8–10.4 dB, respectively. The whole transceiver occupies 3 × 2.3 mm2 chip area including pads.

A 28-GHz eight-element phased-array receiver front-end with compact size in 65-nm CMOS technology for 5G new radio

This article presents an 8-element 24–30-GHz phased-array receiver front-end in 65-nm CMOS technology for the millimeter-wave fifth-generation mobile network (5G). The phased-array receiver front-end is based on the radio-frequency (RF) phase-shifting architecture using RF vector-sum phase shifters with 5-bit phase resolution. The designed front-end can be easily expanded for use in large-scale phased arrays due to its compact size, low manufacturing costs, reasonable power consumption and low complexity. The post-layout simulations show a maximum single-element average gain of 12.85–15.7 dB across 5-bit phase states, with an associated noise figure (NF) of 6.15–7.5 dB and an input third-order intercept point (IIP3) value between –16.5 and –15.4 dBm. The simulated RMS gain and phase errors are less than 0.31 dB and 3°, respectively over 32 phase states and are constant over a 6-bit gain control. The designed eight-element phased-array receiver front-end has a total power consumption of 256±2.5 mW from a 1.2-V supply and occupies a small active area of 0.62 mm2.

60 GHz 7-Bit Passive Vector-Sum Phase Shifter With an X-Type Attenuator

This letter presents the design of a 60 GHz passive vector-sum phase shifter with 7-bit phase resolution. An analog X-type attenuator with complementary voltage control was used for vector modulation. The proposed attenuator is suitable for high-resolution phase shifter design because it is capable of phase inversion and shows a large attenuation range with low-phase variation. The prototype phase shifter fabricated through the 65 nm CMOS process occupies an area of 0.24 mm2 (excluding the bonding pads). The measurement results show that the proposed phase shifter achieves a phase resolution of 2.815∘ while exhibiting an average insertion loss of 14 dB without DC power consumption. The calculated RMS gain and phase error were below 0.55 dB and 0.83-2.36∘, respectively, in the range of 57-67 GHz.

Analysis and Design of a Ku-Band Bidirectional Time-Varying Vector-Sum Phase Shifter in 0.13-μm CMOS Technology

This brief describes a Ku-band passive time-varying phase shifter (TVPS). The time variable is introduced into the conventional vector-sum phase shifter (VSPS) architecture, and the time-varying vector-sum method is proposed for the first time to realize continuous phase shifting. The proof-of-concept passive TVPS consisting of a quadrature coupler, two 0/180° bi-phase modulators and an output combiner is implemented in 0.13- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {\mathrm {\mu }}\text{m}$ </tex-math></inline-formula> CMOS technology with a core area of 2.2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {\times }$ </tex-math></inline-formula> 0.8 mm2, and a field-programmable gate array (FPGA) is used to provide gain-control timing sequences with the modulation frequency of 100 kHz for its four control bits. The timing sequences are optimized to eliminate unwanted sidebands, and the measured sideband suppression ratio (SSR) is −17.2 dBc. For both forward and backward phase shifting modes, measured results show that the proposed TVPS can achieve the phase resolution of 10-bits, RMS phase error of 0.2~0.5°, RMS gain error of less than 0.2 dB over the 12~18 GHz frequency band.

CMOS variable-gain phase shifter based on time-varying vector-sum method and its application to Ku-band phased array

In this paper, a new time-varying vector-sum method is proposed for variable-gain phase shifter design. By introducing a time variable into the conventional vector-sum phase shifter (VSPS) architecture, high-resolution phase shifting and wide amplitude control can be achieved simultaneously. The proposed time-varying phase shifter (TVPS) is fabricated in 0.13-μm CMOS technology with a core area of 1.76 mm2. A field-programmable gate array (FPGA) is utilized to generate gain-control timing sequences for phase shifting and on-off timing sequence for amplitude control, which are optimized to achieve a measured sideband suppression ratio of −17.2 dBc. For bidirectional operation, measured results present that the proposed TVPS can achieve a phase resolution of 10-bits, RMS (root mean square) phase error of 0.2–0.5°, RMS gain error of less than 0.2 dB, and gain tuning range of 10.1 dB in the frequency band of 12–18 GHz. The proposed TVPS is applied to a 4-element phased array, and the measured radiation patterns of scanned beams are presented.

A Hybrid True-Time and Phase-Delayed Approach for Millimeter-Wave Beam Steering

In this research study, a novel hybrid approach to beam steering based on the combination of true time delay and phase shift to enable continuous beam steering with minimal beam squint in wideband mm-wave transceivers is investigated. With modern high-speed communication links in the mm-wave spectrum requiring ever higher bandwidths, and losses increasing with frequency, there is a need for steerable arrays in mobile applications. This steering capability is commonly realized by phase shifters, which enable continuous beam direction control, but produce significant beam squint at large bandwidths or steering directions. An alternative is to use a time-delayed control, which resolves the squint issue but covers only a limited number of beam directions, producing considerable loss and being large in size. This research work presents the first 2-bit time delay stage operating above 200 GHz. In addition, a novel approach is described to enable broadband continuous beam control with minimal beam squint; this is achieved by combining the time delay circuit with a 90° vector-sum phase shifter. To prove the concept, the circuit is realized in a 130-nm SiGe Bipolar Complementary Metal Oxide Semiconductor (CMOS) (BiCMOS) technology. At 4.33 mW of dc power consumption, the small-signal gain is −8.6 dB at a 3-dB band of 220–250 GHz, resulting in 12.8% of relative bandwidth. The time delay stage provides coarse beam direction control with a maximum steering angle of 43.9° resulting from a maximum delay of 1.47 ps with a resolution of 0.39 ps. Across all tuning states, the root-mean-square delay error is less than 23.7 fs. The following phase shifter enables fine direction control while also compensating ±1.5 dB of gain variation resulting from the time delay. This is achieved while reducing the area consumption to half of what is required for comparable true time delay circuits. In a minimal <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times 1$ </tex-math></inline-formula> antenna array, this enables continuous beam direction control between ±54.6° while limiting the beam squint to less than 2.5°, equating to a more than 75% reduction in comparison to the common phase shift approach.

A 4–10 GHz Programmable CMOS Vector-Sum Phase Shifter for a Two-Channel Transmitter

A 6-bit full-span programmable vector-sum phase shifter was presented in this brief. A transformer-based matching network is used to match the PPF-based I/Q generator to the variable gain amplifier-based vector-modulator (VGA-based VM), which eliminates the performance degradation due to impedance mismatch. The proposed phase shifter integrated in a two-channel transmitter was implemented in a 180-nm CMOS process. A program-assisted method was used to select the desired 6-bit (64) phase states from the total 4096 measured states of the chip, to realize a highly accurate phase tuning. The center frequency of the phase tuning can be set in the program, for different operation frequency points. An ultra-low root-mean-square (rms) phase/gain error less than 0.5°/0.15 dB are obtained at corresponding single frequency points. Moreover, a “band” mode is available as well, and rms phase/gain errors less than 2.25°/0.56 dB and 1.1°/0.32 dB are obtained at 4–10 GHz and 5.5-7.5 GHz, respectively.

A Simplified Vector-Sum Phase Shifter Topology With Low Noise Figure and High Voltage Gain

An simplified vector-sum phase shifter (VSPS) topology is proposed in this article. The proposed VSPS topology employs only one 90° coupler to perform as both an I/Q generator and a vector summer. Compared with the literaturally reported VSPS, the proposed VSPS features a simpler topology and improved noise figure (NF) performance. Moreover, active baluns based on the self-calibration technique are employed to provide antiphase signals and improve the gain performance of the VSPS. For demonstration, a 24–30-GHz VSPS based on the proposed topology is implemented in the 65-nm CMOS process, exhibiting 3.5° rms phase error and 0.9-dB rms gain error. The average gain of the implemented VSPS is as high as 9 dB at the central frequency of 27 GHz. The NF ranges from 4.8 to 9 dB from 24 to 30 GHz, and the core chip size is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.36\times0.59$ </tex-math></inline-formula> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

An Integrated Compact Phase Shifter With a Single Analog Control

This letter presents a new circuit topology for a vector sum phase shifter where the amplitudes and phases of I and Q are simultaneously varied using a single analog control signal. The simultaneous adjustment of amplitudes and phases of I and Q allows for the vector sum's large phase tuning while maintaining its amplitude. Moreover, various functions of vector summation are all performed in a single stage, minimizing the chip real estate and power consumption. The maximum range of analog phase tuning with a constant amplitude is theoretically 180°, but in practice, it is limited by the tuning range of the utilized varactors. To achieve a large phase tuning range given varactors with limited tunability, digital control has been added to allow for coarse tuning of the phase. The utilized approach for coarse phase tuning preserves the chip area and power consumption but causes amplitude variation. The phase shifter performance is verified by simulations and measurements.

A 60-GHz Variable-Gain Phase Shifter With Particular-Sized Digital-RF Cells

A 60-GHz variable-gain active phase shifter using particular-sized digital-RF cells is proposed, which is fabricated using a 65-nm CMOS process. The phase shifter consists of an input buffer, an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I/Q$ </tex-math></inline-formula> generator, and vector-summing amplifiers with digital-RF cells. In a vector-sum phase shifter using a conventional tail current steering scheme, the operation regions of vector-summing amplifiers are changed with phase and gain states. Accordingly, their input impedances are altered significantly, which causes gain and phase imbalances of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I/Q$ </tex-math></inline-formula> generator, especially around 0°, 90°, 180°, and 270°. This makes the rms phase and gain errors of the phase shifter increase. In this article, a vector-summing amplifier that always has a constant input impedance in all phases and gain states is proposed. A circular constellation and a dynamic range of more than 15 dB are implemented by using particular-sized digital-RF cells. The proposed phase shifter shows the rms gain and phase errors of < 0.29 dB and <2.01°, respectively, in a 10-GHz bandwidth of 55–65 GHz with 3-bit gain and 4-bit phase resolutions. The chip area and power consumption are 0.38 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 25.2 mW, respectively.

Novel Passive Vector-Sum Reconfigurable Filtering Phase Shifter With Continuous Phase-Control and Tunable Center Frequency

In this article, a novel reconfigurable filtering vector-sum phase shifter (RFPS) with a continuous phase shift range of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\ge 300^{\circ }$ </tex-math></inline-formula> and tunable operating frequency range from 1.05 to 1.3 GHz is proposed. It consists of two identical wideband Wilkinson power dividers (or power combiners) (WPDs) and a reconfigurable filtering quadrature coupler (RFQC) that is connected between the two WPDs. Through the first WPD, the split waves are fed into the RFQC and are then combined at the output ports of the RFQC. The phase of the combined waves can be continuously tuned by adjusting different combinations of coupling types between interstage resonators of the RFQC, and the resulted output waves are then summed up through the second WPD with the desired output phase. Different from the conventional active vector-sum phase shifter, the vector summing is realized by the proposed RFQC and is a pure passive design, resulting in a low-cost, low-noise, easy-design, and highly flexible system. A prototype is designed and fabricated to demonstrate the proposed technique. Detailed theoretical analysis and design procedure have been given. The experimental results show that the proposed RFPS features the continuous phase-control range of more than 300° with a tunable filtering response covering the frequency range from 1.05 to 1.3 GHz.

A CMOS Vector-Sum Phase Shifter for 5G mm-Wave Application

This paper presents a wideband CMOS vector-sum phase shifter (VSPS) targeting the n260 band of 5G communication. A differential quadrature generator is implemented using a Marchand balun and two 90° coupled-line couplers to improve robustness to process and temperature variations. The quadrature vector signals are combined by a following vector modulator that adopts a double Gilbert-cell topology. The linearity and input-matching performance are enhanced at the expense of extra DC consumption by stacking a current source with high bias. The measurement shows that the VSPS provides a continuous 360° phase shift with an average insertion loss of 16.3 dB at 37 GHz. The root-mean-square (RMS) amplitude and phase errors maintain less than 1.5 dB and 4.9°, respectively, from 30.9 GHz to 41.7 GHz. The input-referred 1-dB compression point is 5.7 dBm at 38 GHz. It is also demonstrated by 484-state measurement that the phase and amplitude can be adjusted in a fine resolution.

2 × 4 VGA-Less Bidirectional Dual-Polarization 28 GHz Beamformer in 130-nm SiGe BiCMOS

This letter presents a dual-polarization beamformer chip for fifth-generation (5G) applications. The chip leverages a vector-sum phase shifter (VSPS) approach and single-ended design, allowing a reduced control circuitry complexity. The use of the VSPS translates in both phase shift and gain control, as shown in the system analysis. This beamformer is suitable for four dual-polarized antennas, achieving high gain control for each element. The performance can be summarized as a 1-dB compression point of 11dBm, while having an rms phase and amplitude error lower than 0.5° and 0.4 dB, respectively, at the maximum constant magnitude gain circle. Moreover, it is shown that the design can afford tapering despite relying only on the VSPS for gain control.

A 15–38 GHz Vector-Summing Phase-Shifter With 360° Phase-Shifting Range Using Improved I/Q Generator

This brief presents a 15–38 GHz vector-summing phase shifter (VSPS) with the full 360° phase-shifting range in the 65nm CMOS process. An improved wideband quadrature all-pass filter (QAF) is designed to overcome the traditional one’s capacitive loading effect and exhibits wideband I/Q performance. Analysis and comparison between the proposed QAF and the traditional one are discussed. For demonstration, a prototype VSPS with the full 360° phase-shifting range from 15GHz to 38GHz using the proposed QAF is implemented in the 65nm CMOS process. The root means square (RMS) phase and gain errors are 2°~3.5° and 0.7 dB ~1 dB from 15 GHz to 38 GHz, respectively. The power consumption is 19.2mW, and the whole chip is compact with a core size of 0.16mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

High-Resolution Wideband Vector-Sum Digital Phase Shifter With On-Chip Phase Linearity Enhancement Technology

In this paper, a wideband vector-sum phase shifter with phase linearity enhancement technology is proposed to minimize phase error. The digital phase shifter synthesizes the output phases by modulating and summing four quadrature signals. A common-source stage with transformer-based matching network and a quadrature-all-pass filter (QAF) are utilized for the quadrature signals generation within a wideband. Besides, to decrease the influence of parasitics on amplitude and phase error, a resistor-based compensation technology is employed in the QAF implementation. Then, to obtain the 360° range high resolution phase shifts, the quadrature signals are modulated by four Gilbert-type variable gain amplifiers (VGAs) with digital-controlled current-digital to analog converters (current-DACs). To further minimize phase error, an on-chip phase linearity enhancement loop is utilized. The drain voltages of current-DACs are detected and compared to the presupposed reference voltages generated by the loop. Besides, the compared results are fed back to control the current-DACs to achieve phase linearity enhancement. To verify the mentioned mechanism, a 7-bit digital phase shifter operating at 22-44 GHz with on-chip phase linearity enhancement technology is implemented and fabricated in a 28-nm CMOS technology. Based on the phase linearity enhancement technology, the phase shifter exhibits a RMS amplitude error of 0.36-0.59 dB and RMS phase error of 0.92° -1.02° without off-chip digital pre-distortion (DPD) technology. The total DC power consumption including the phase linearity enhancement loops is 35 mW under a 0.9V supply voltage.

Phase shifters with multiple independently controllable bands utilising frequency‐selective variable gain networks

A dual-band vector-sum phase shifter with independent phase control of the 2.4 and 5 GHz Wi-Fi bands is presented. The network uses band-limited variable gain amplification, with a broadband hybrid coupler at the input and an in-phase recombiner at the output. The circuit is prototyped on RF printed circuit board and exhibits performance characteristics comparable to the state-of-the-art single band vector-sum phase shifters. The prototype achieved an average gain of 2.16 dB over the 2.4 GHz band, with less than 0.26 dB and 1.32° root-mean-square (RMS) gain and phase error across all 2.4 and 5 GHz band tuning states. In the 5 GHz band, an average gain of 0.17 dB is achieved, with less than 0.21 dB and 3.88° RMS gain and phase error. The network's ability to generate band-independent vector modulation over a 12 dB/90° tuning range is demonstrated as well, achieving less than 0.12 dB and 0.27° RMS gain and phase error in the 2.4 GHz band, and less than 0.27 dB and 2.94° gain and phase error in the 5 GHz band.

Vector-Sum Phase Shifter Using a Tunable Active g m -C Polyphase Filter

We have proposed a vector-sum phase shifter (VSPS) with a low phase shift error using a tunable active $g_{m}{\text {-}}{C}$ polyphase filter (PPF). The proposed VSPS realizes high insertion gain and a low phase shift error because the tunable active ${g}_{m}{\text {-}}{C}$ PPF exhibits insertion gain and low I/Q imbalance by easily controlling the transconductance of transistors. This study provides a general formula and design method based on the design equations of the tunable active ${g}_{m}{\text {-}}{C}$ PPF for VSPS. The analysis shows the limitation of the tunable frequency range of I/Q balance and the condition of the maximum insertion gain. The results also clarify that the relative bandwidth of the tunable active ${g}_{m}{\text {-}}{C}$ PPF is equivalent to that of the single-stage or multistage RC -PPF. The ${S}$ -band VSPS with the two-stage active ${g}_{m}{\text {-}}{C}$ PPF fabricated by the design method demonstrates improvement in phase shift errors lower than 0.52° rms in the 500-MHz bandwidth and high insertion gain of 13.4 dB with a frequency range of 2.2–3.2 GHz.

A 60-GHz Low-Power Active Phase Shifter With Impedance-Invariant Vector Modulation in 65-nm CMOS

This study presents the design and analysis of a 60-GHz low-power active vector-sum phase shifter with 5-bit phase resolution. An impedance-invariant variable gain amplifier (VGA) is proposed and applied to the vector modulator. The proposed VGA not only demonstrates low phase and impedance variations during gain control but also high linearity under low supply voltage. Moreover, it reduces the gain/phase error in vector modulation. In addition, the transformer-based current-reuse technique is adopted to enhance the gain of the phased array channel while consuming low dc power. The prototype circuit implemented in 65-nm CMOS technology consumes only 5 mW of dc power and occupies an area of 0.3 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (excluding pads). The measurement results of the prototype circuit reveal that the proposed phase shifter achieves an average gain of -3.8 dB (including a 2-dB loss of the measurement balun), an rms gain error of 0.25-0.72 dB, and an rms phase error of 3°-7° in the 3-dB bandwidth from 51 to 66.3 GHz. The measured input 1-dB compression point is observed to be higher than -1.1 dBm at 60 GHz.