Vector Based Pulse Width Modulation Research Articles

A New Configuration of Three-Level ZSI Using Transistor Clamped Topology

In this paper, a three-level ZSI (impedance source inverter) based on transistor clamped theory is proposed. It uses the least number of switch counts and associated gate circuitry among all existing topologies of three-level ZSI without any performance degradation. The existing three-level ZSI topologies require three power switches to be turned ON for upper-lower shoot-through (ULST), and four power switches to be turned ON for full dc-link shoot-through (FST). However, with the proposed configuration, upper–lower shoot-through (ULST) and full dc-link shoot-through (FST) is inserted by turning ON only two power semiconductors. A comparison between diode clamped, transistor clamped, and t-type is presented. The proposed topology can realize any of the existing sine-triangle- or space vector-based PWM (pulse width modulation) schemes, and all existing configurations of three-level ZSI can merge into the proposed inverter configuration.

An Efficient Digital Space Vector PWM Module for 3-φ Voltage Source Inverter (VSI) on FPGA

The realization of digital control circuitry based PWM strategies provides many advantages. It includes better prototyping, higher switching frequency, simple hardware, and flexibility by overcoming the limitations of analog control strategies. In this article, The Digital space vector-based Pulse width Modulation ((DSV-PWM) is designed. The DSV-PWM Module includes, mainly, Xdq reference frame, Sector generation, Square root, switching time generation, Carry-save adder (CSA), and PWM Generation module. These modules are designed using simple logical operations, and combinational circuits to improve the DSV-PWM performance. The DSV-PWM Module is synthesized and implemented on a cost-effective Artix-7 FPGA device. The present work utilizes a < 1% chip area, operates at 597.83 MHz of maximum frequency, and utilizes 110mW of total power on FPGA Device. The DSV-PWM module is also compared with the existing SV-PWM approach with better improvement in hardware constraints like chip area, operating frequency, and dynamic power (mW).

Effect of center voltage vectors (CVVs) of three-level space plane on the performance of dual inverter fed open end winding induction motor drive

Dual inverter fed open end winding induction motor (IM) drive offers many advantages over other multilevel inverter fed IM drives. Pulse width modulation (PWM) techniques are employed for the control of output voltage and frequency. Space vector base PWM techniques are popular among all the PWM techniques. A simplified space vector PWM method with simple and small look-up table approach is presented for dual inverter configuration. Moreover the proposed space vector based PWM technique provides freedom in selecting the center voltage vector (CVV) by which different PWM techniques will be derived. The implementation of all these PWM techniques is generalized by using a constant a <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</sub> . The derived PWM techniques show superior performance in reducing the zero sequence voltage (ZSV) by maintaining the same quality of output voltage. The performance of all these PWM techniques are evaluated theoretically and verified in real time through dSPACE 1104 control board.

Asymmetric Cascaded Inverter for Photovoltaic Applications Based on Carrier Redistribution Modulation Strategies

Asymmetric Cascaded Multilevel inverter (ACMLI) for photovoltaic (PV) generating system is presented in this paper. The proposed asymmetrical arrangements of seven-level cascaded inverters have been compared with advanced modulation strategies, in order to find an optimum arrangement with lower harmonic distortion and optimized output voltage quality and which makes use of minimum number of switches to get more levels. It also reduces the complexity, number of sources, cost and losses. Modulating control techniques can be modified in two ways, namely Modified Carrier (MC) and Modified Reference (MR). This paper proposes modifies space vector based pulse width modulation (PWM) using various U-type Carrier Redistribution Methods (CRM) which utilize the control freedom degree (CFD) of vertical offsets among carriers and also compared with existing sinusoidal PWM technique for single-phase seven level ACMLI using MATLAB/Simulink.

Space vector based random pwm algorithms for acoustic noise and harmonics reduction for voltage source inverter fed ac drive

Conventional Space vector based Pulse Width Modulation (PWM) method is superior to Sinusoidal PWM technique in terms of its better DC bus utilization as well as harmonic reduction. But it doesn’t give solution to reduce acoustic noise which is more annoyance to the driver and the passenger or the human beings in certain applications such as electric propulsion or accessory drives. This paper presents space vector based random PWM techniques - a solution to reduce the acoustic noise as well spread spectrum resulting in low harmonic distortion as suppression of peak sound pressure levels. The techniques employed for a VSI fed Induction motor drive are 1) Random Zero vector PWM 2) Dual Zero Random PWM and 3) Variable Delay Random PWM. The spectrum plots of stator current demonstrate the effectiveness of the proposed PWM techniques. The feasibility of the proposed PWM techniques has been confirmed in terms of acoustical noise and harmonic distortion is presented in this paper.

Space vector‐based three‐level discontinuous pulse‐width modulation algorithm

Discontinuous pulse-width modulation (PWM) techniques result in reduced power loss in voltage source inverters. This study presents the space vector approach to the three-level discontinuous PWM technique. The switching sequences for four basic types of discontinuous PWM and the implementation are presented. An improved discontinuous PWM algorithm is presented for low modulation index region. All these algorithms are verified experimentally and the results are presented. The performance of discontinuous PWM algorithms is compared with that of conventional space vector-based PWM algorithms.

Medium Voltage Drive for Induction Motors Using Multilevel Octadecagonal Voltage Space Vectors

Multilevel inverters with hexagonal and dodecagonal voltage space vector structures have improved harmonic profile compared to two-level inverters. Further improvement in the quality of the waveform is possible using multilevel octadecagonal (18-sided polygon) voltage space vectors. This paper proposes an inverter circuit topology capable of generating multilevel octadecagonal voltage space vectors, by cascading two asymmetric three-level inverters. By the proper selection of dc-link voltages and the resultant switching states for the inverters, voltage space vectors, whose tips lie on three concentric octadecagons, are obtained. The advantages of octadecagonal voltage space vector-based pulsewidth modulation (PWM) techniques are the complete elimination of fifth, seventh, eleventh, and thirteenth harmonics in phase voltages and the extension of linear modulation range. In this paper, a simple PWM timing calculation method is also proposed. Experimental results have been presented in this paper to validate the proposed concept.

Space-vector-based hybrid pulse width modulation technique to reduce line current distortion in induction motor drives

Pulse width modulation (PWM) techniques involving different switching sequences are used in space vector-based PWM generation for reducing line current ripple in induction motor drives. This study proposes a hybrid PWM technique employing five switching sequences. The proposed technique is a combination of continuous PWM, discontinuous PWM (DPWM) and advanced bus clamping PWM methods. Performance of the proposed PWM technique is evaluated and compared with those of the existing techniques on a constant volts per hertz induction motor drive. In terms of total harmonic distortion in the line current, the proposed method is shown to be superior to both conventional space vector PWM (CSVPWM) and DPWM over a fundamental frequency range of 32–50 Hz at a given average switching frequency. The reduction in harmonic distortion is about 42% over CSVPWM at the rated speed of the drive.

Effect of Zero-Vector Placement in a Dual-Inverter Fed Open-End Winding Induction Motor Drive With Alternate Sub-Hexagonal Center PWM Switching Scheme

Three-level inversion can be achieved by the cascade connection of two two-level inverters to an open-end winding induction motor. Several space vector based pulsewidth modulation (PWM) control strategies have been proposed for this power circuit configuration in the past. It is known that space vector modulation offers a degree of freedom in its implementation with regard to the distribution of the zero-vector. In this paper, the effect of placement of zero-vector for the implementation of space vector based PWM techniques for a dual-inverter fed open-end winding induction motor drive is reported. Apart from constructing a consistent theoretical frame work, experimental results with continuous and discontinuous PWM are presented in this paper and all the cases are compared.

A circulating current control scheme for multiple three‐level NPC inverter systems

AbstractIn recent years, motor drive systems for steel rolling mills have been steadily increasing in capacity. In particular, the development of three‐level NPC (Neutral Point Clamped) inverters is now focusing on the replacement of cycloconverters. In order to satisfy such a requirement, in this paper a multiple three‐level NPC inverter system is proposed. The configuration consists of two three‐level NPC inverters with the same configuration connected in parallel by current limiting reactors. In this case, the circulating current flowing between the two three‐level NPC inverters must be controlled to prevent a decrease in the maximum output capacity. In particular, a new method for control of the circulating current is a major topic of discussion. The method is based on space voltage vector‐based PWM (Pulse Width Modulation) control for the three‐level NPC inverters and the circulating current is controlled by adjusting the output durations of the respective space voltage vectors. In this method the circulating current controller can be decoupled from the motor current controller. Therefore, it is possible to design the different controllers independently. In addition, the experimental results obtained using an induction motor show that the circulating current can be reduced to within 2% of the rated motor current when the motor current response exceeds 1000 rad/s. © 2001 Scripta Technica, Electr Eng Jpn, 136(2): 38–48, 2001