Variety Of Hardware Platforms Research Articles

Software-Bus-Toolchain (SBT): Introducing a Versatile Method for Quickly Implementing (I)IoT-Scenarios

The Internet of Things (IoT) has become ubiquitous. IoT devices are applied in a multitude of applications, e.g., in smart home scenarios, building automation, smart energy and smart cities, healthcare, and industrial environments. Fast and efficient implementation and roll-out of IoT devices is a critical factor for successs and acceptance of IoT devices. At the same time, the variety of hardware platforms that can be used for IoT applications, as well as the number of IoT orchestration platforms is increasing. Finding the right combination of tooling and hardware is not trivial, but essential for building applications that provide value. In this work, a Software-Bus-Toolchain (SBT) is introduced that encapsulates firmware design, data point definition, and communication protocol usage. Furthermore, an IoT control platform is provided to control and evaluate the IoT modules. Thus, using the SBT, solely the business logic has to be designed, while the hardware-design is automated to a high degree. Usage of the Zephyr framework allows the interchange of hardware modules, while interfaces provide easy adaption of data points and communication capabilities. The implementation of interfaces to the IoT-platform as well as to the communication layer provides a universal usage of logic and data elements. The SBT is evaluated in two application scenarios, where its flexible nature is shown.

A high-fidelity quantum matter-link between ion-trap microchip modules

System scalability is fundamental for large-scale quantum computers (QCs) and is being pursued over a variety of hardware platforms. For QCs based on trapped ions, architectures such as the quantum charge-coupled device (QCCD) are used to scale the number of qubits on a single device. However, the number of ions that can be hosted on a single quantum computing module is limited by the size of the chip being used. Therefore, a modular approach is of critical importance and requires quantum connections between individual modules. Here, we present the demonstration of a quantum matter-link in which ion qubits are transferred between adjacent QC modules. Ion transport between adjacent modules is realised at a rate of 2424 s−1 and with an infidelity associated with ion loss during transport below 7 × 10−8. Furthermore, we show that the link does not measurably impact the phase coherence of the qubit. The quantum matter-link constitutes a practical mechanism for the interconnection of QCCD devices. Our work will facilitate the implementation of modular QCs capable of fault-tolerant utility-scale quantum computation.

Modernizing the NEURON Simulator for Sustainability, Portability, and Performance.

The need for reproducible, credible, multiscale biological modeling has led to the development of standardized simulation platforms, such as the widely-used NEURON environment for computational neuroscience. Developing and maintaining NEURON over several decades has required attention to the competing needs of backwards compatibility, evolving computer architectures, the addition of new scales and physical processes, accessibility to new users, and efficiency and flexibility for specialists. In order to meet these challenges, we have now substantially modernized NEURON, providing continuous integration, an improved build system and release workflow, and better documentation. With the help of a new source-to-source compiler of the NMODL domain-specific language we have enhanced NEURON's ability to run efficiently, via the CoreNEURON simulation engine, on a variety of hardware platforms, including GPUs. Through the implementation of an optimized in-memory transfer mechanism this performance optimized backend is made easily accessible to users, providing training and model-development paths from laptop to workstation to supercomputer and cloud platform. Similarly, we have been able to accelerate NEURON's reaction-diffusion simulation performance through the use of just-in-time compilation. We show that these efforts have led to a growing developer base, a simpler and more robust software distribution, a wider range of supported computer architectures, a better integration of NEURON with other scientific workflows, and substantially improved performance for the simulation of biophysical and biochemical models.

TSF-DBSCAN: A Novel Fuzzy Density-Based Approach for Clustering Unbounded Data Streams

In recent years, several clustering algorithms have been proposed with the aim of mining knowledge from streams of data generated at a high speed by a variety of hardware platforms and software applications. Among these algorithms, density-based approaches have proved to be particularly attractive, thanks to their capability of handling outliers and capturing clusters with arbitrary shapes. The streaming setting poses additional challenges that need to be addressed as well: data streams are potentially unbounded and affected by concept drift, i.e., a modification over time in the underlying data generation process. In this article, we propose temporal streaming fuzzy density-based spatial clustering of applications with noise (TSF-DBSCAN), a novel fuzzy clustering algorithm for streaming data. TSF-DBSCAN is an extension of the well-known DBSCAN algorithm, one of the most popular density-based clustering approaches. Fuzziness is introduced in TSF-DBSCAN to model the uncertainty about the distance threshold that defines the neighborhood of an object. As a consequence, TSF-DBSCAN identifies clusters with fuzzy overlapping borders. A fading model, which makes objects less relevant as they become more remote in time, endows TSF-DBSCAN with the capability of adapting to evolving data streams. The integration of the model in a two-stage approach ensures computational and memory efficiency: during the online stage, continuously arriving objects are organized in proper data structures that are later exploited in the offline stage to determine a fine-grained partition. An extensive experimental analysis on synthetic and real-world datasets shows that TSF-DBSCAN yields competitive performance when compared to other clustering algorithms recently proposed for streaming data.

Wattsworth: An Open-Source Platform for Decentralized Sensor Networks

Internet of Things (IoT) sensor networks have the potential to deliver major benefits across a wide variety of industries, but designing the necessary data collection, processing, and presentation infrastructure can make them cost prohibitive. This has led to a Faustian bargain with centralized vendors who offer platform-as-a-service (PaaS) IoT solutions. Customers cede control of their sensors and all data they collect to a third party in exchange for convenient analytics. This type of perpetual subscription is a compelling revenue model that has stifled industry innovation in alternative architectures. This article presents Wattsworth, an open-source, decentralized alternative to PaaS-based IoT. Data collection, processing, and presentation are distributed across the network using a modular architecture. Lightweight “Data Apps” provide customizable user interfaces ensuring the information is relevant and actionable. Case studies of Wattsworth deployments across a variety of hardware platforms from single board computers to cloud-based servers demonstrate its utility in decentralized IoT applications. Full documentation, source code, and installation media are available online at https://wattsworth.net .

PyPaSWAS: Python-based multi-core CPU and GPU sequence alignment.

BackgroundOur previously published CUDA-only application PaSWAS for Smith-Waterman (SW) sequence alignment of any type of sequence on NVIDIA-based GPUs is platform-specific and therefore adopted less than could be. The OpenCL language is supported more widely and allows use on a variety of hardware platforms. Moreover, there is a need to promote the adoption of parallel computing in bioinformatics by making its use and extension more simple through more and better application of high-level languages commonly used in bioinformatics, such as Python.ResultsThe novel application pyPaSWAS presents the parallel SW sequence alignment code fully packed in Python. It is a generic SW implementation running on several hardware platforms with multi-core systems and/or GPUs that provides accurate sequence alignments that also can be inspected for alignment details. Additionally, pyPaSWAS support the affine gap penalty. Python libraries are used for automated system configuration, I/O and logging. This way, the Python environment will stimulate further extension and use of pyPaSWAS.ConclusionspyPaSWAS presents an easy Python-based environment for accurate and retrievable parallel SW sequence alignments on GPUs and multi-core systems. The strategy of integrating Python with high-performance parallel compute languages to create a developer- and user-friendly environment should be considered for other computationally intensive bioinformatics algorithms.

Endpoint Security in Networks: An OpenMP Approach for Increasing Malware Detection Speed

Increasingly sophisticated antivirus (AV) software and the growing amount and complexity of malware demand more processing power from personal computers, specifically from the central processor unit (CPU). This paper conducted performance tests with Clam AntiVirus (ClamAV) and improved its performance through parallel processing on multiple cores using the Open Multi-Processing (OpenMP) library. All the tests used the same dataset constituted of 1.33 GB of data distributed among 2766 files of different sizes. The new parallel version of ClamAV implemented in our work achieved an execution time around 62% lower than the original software version, reaching a speedup of 2.6 times faster. The main contribution of this work is to propose and implement a new version of the ClamAV antivirus using parallel processing with OpenMP, easily portable to a variety of hardware platforms and operating systems.

Scalpel

As the size of Deep Neural Networks (DNNs) continues to grow to increase accuracy and solve more complex problems, their energy footprint also scales. Weight pruning reduces DNN model size and the computation by removing redundant weights. However, we implemented weight pruning for several popular networks on a variety of hardware platforms and observed surprising results. For many networks, the network sparsity caused by weight pruning will actually hurt the overall performance despite large reductions in the model size and required multiply-accumulate operations. Also, encoding the sparse format of pruned networks incurs additional storage space overhead. To overcome these challenges, we propose Scalpel that customizes DNN pruning to the underlying hardware by matching the pruned network structure to the data-parallel hardware organization. Scalpel consists of two techniques: SIMD-aware weight pruning and node pruning. For low-parallelism hardware (e.g., microcontroller), SIMD-aware weight pruning maintains weights in aligned fixed-size groups to fully utilize the SIMD units. For high-parallelism hardware (e.g., GPU), node pruning removes redundant nodes, not redundant weights, thereby reducing computation without sacrificing the dense matrix format. For hardware with moderate parallelism (e.g., desktop CPU), SIMD-aware weight pruning and node pruning are synergistically applied together. Across the microcontroller, CPU and GPU, Scalpel achieves mean speedups of 3.54x, 2.61x, and 1.25x while reducing the model sizes by 88%, 82%, and 53%. In comparison, traditional weight pruning achieves mean speedups of 1.90x, 1.06x, 0.41x across the three platforms.

Balancing Energy and Performance in Dense Linear System Solvers for Hybrid ARM+GPU platforms

The high performance computing community has traditionally focused uniquely on the reduction of execution time, though in the last years, the optimization of energy consumption has become a main issue. A reduction of energy usage without a degradation of performance requires the adoption of energy-efficient hardware platforms accompanied by the development of energy-aware algorithms and computational kernels. The solution of linear systems is a key operation for many scientific and engineering problems. Its relevance has motivated an important amount of work, and consequently, it is possible to find high performance solvers for a wide variety of hardware platforms. In this work, we aim to develop a high performance and energy-efficient linear system solver. In particular, we develop two solvers for a low-power CPU-GPU platform, the NVIDIA Jetson TK1. These solvers implement the Gauss-Huard algorithm yielding an efficient usage of the target hardware as well as an efficient memory access. The experimental evaluation shows that the novel proposal reports important savings in both time and energy-consumption when compared with the state-of-the-art solvers of the platform.

Video surveillance and counterterrorism: the application of suspicious activity recognition in visual surveillance systems to counterterrorism

Video surveillance systems have become a key element in efforts by security services, the military and law enforcement to counterterrorism since the attacks of 11 September 2001. Primarily involving closed circuit television, collected using a variety of hardware platforms and software algorithms, systematic imagery analysis has typically been used as a tool for post-event forensics to identify tactics, techniques and perpetrators of terrorist attacks. Advanced video surveillance applied to detecting suspicious behaviours embedded in crowd signatures can also be a powerful tool for pre-event deterrence. In this article, we examine case studies of attempts by terrorists to target civilians and create mass casualty incidents and evaluate existing behaviour detection algorithms with the goal of elucidating links between potential threats indicated by suspicious behaviours and possible deterrent mechanisms based on video surveillance.

From the Editor's Desk

This issue features several articles that give different perspectives on the emergence of affordable computers for use by ordinary people. Specifically, Kevin Gotkin's "When Computers Were Amateur" and Petri Saarikoski and Markku Reunanen's "Great Northern Machine Wars: Rivalry Between User Groups in Finland" look at the history of amateur computing from the perspective of the users, rather than that of the manufacturers or by focusing on technological artifacts. The issue also includes a discussion of the 1940s effort to convert ENIAC to the new style of programming first described in John von Neumann's "First Draft of a Report on the EDVAC" and an article by David Walden and his team of contributors that documents the emergence of the Arpanet Interface Message Processor (IMP) program and how it evolved to run on a variety of hardware platforms.

The Arpanet IMP Program: Retrospective and Resurrection

People from Bolt Beranek and Newman and others have extensively documented the Arpanet technology, including the Arpanet Interface Message Processor (IMP). This paper sketches the history (not the previously described technology) of the IMP program as originally written in 1969 for the modified Honeywell 516 computer. A sequence of other systems, evolving from the original software system and running on a variety of hardware platforms, are also enumerated. In 2013 a faded 1973 line printer listing of the IMP program was run through a special OCR program optimized to process such historical artifacts; an assembler was recreated to assemble the IMP code (looking like the modified PDP-1 Midas assembler used in 1973); and a software emulator of the original IMP hardware platform was created. This article also describes the methods used to recover a digital copy and assemble and run again the 1973 IMP code.

A Unified Sparse Matrix Data Format for Efficient General Sparse Matrix-Vector Multiplication on Modern Processors with Wide SIMD Units

Sparse matrix-vector multiplication (spMVM) is the most time-consuming kernel in many numerical algorithms and has been studied extensively on all modern processor and accelerator architectures. However, the optimal sparse matrix data storage format is highly hardware-specific, which could become an obstacle when using heterogeneous systems. Also, it is as yet unclear how the wide single instruction multiple data (SIMD) units in current multi- and many-core processors should be used most efficiently if there is no structure in the sparsity pattern of the matrix. We suggest SELL-C-sigma, a variant of Sliced ELLPACK, as a SIMD-friendly data format which combines long-standing ideas from General Purpose Graphics Processing Units (GPGPUs) and vector computer programming. We discuss the advantages of SELL-C-sigma compared to established formats like Compressed Row Storage (CRS) and ELLPACK and show its suitability on a variety of hardware platforms (Intel Sandy Bridge, Intel Xeon Phi and Nvidia Tesla K20) for a wide range of test matrices from different application areas. Using appropriate performance models we develop deep insight into the data transfer properties of the SELL-C-sigma spMVM kernel. SELL-C-sigma comes with two tuning parameters whose performance impact across the range of test matrices is studied and for which reasonable choices are proposed. This leads to a hardware-independent ("catch-all") sparse matrix format, which achieves very high efficiency for all test matrices across all hardware platforms.

OpenMM: A Hardware Independent Framework for Molecular Simulations.

The wide diversity of computer architectures today requires a new approach to software development. OpenMM is a framework for molecular mechanics simulations, allowing a single program to run efficiently on a variety of hardware platforms.

Experiences Using Hybrid MPI/OpenMP in the Real World: Parallelization of a 3D CFD Solver for Multi-Core Node Clusters

Today most systems in high-performance computing (HPC) feature a hierarchical hardware design: shared-memory nodes with several multi-core CPUs are connected via a network infrastructure. When parallelizing an application for these architectures it seems natural to employ a hierarchical programming model such as combining MPI and OpenMP. Nevertheless, there is the general lore that pure MPI outperforms the hybrid MPI/OpenMP approach. In this paper, we describe the hybrid MPI/OpenMP parallelization of IR3D (Incompressible Realistic 3-D) code, a full-scale real-world application, which simulates the environmental effects on the evolution of vortices trailing behind control surfaces of underwater vehicles. We discuss performance, scalability and limitations of the pure MPI version of the code on a variety of hardware platforms and show how the hybrid approach can help to overcome certain limitations.

Evolutionary speech quality estimation in VoIP

Estimating the quality of Voice over Internet Protocol (VoIP) as perceived by humans is considered a formidable task. This is partly due to the relatively large number of variables that are involved as determinants of quality. Moreover, discerning the significance of one variable over the other is difficult. In this paper a novel approach based on genetic programming (GP) is presented. It maps the effect of network traffic parameters on listeners’ perception of speech quality. The ITU-T Recommendation P.862 (PESQ) algorithm is used as a reference model in this research. The GP discovered models that provide effective VoIP quality estimation are highly correlated to ITU-T Recommendation P.862 (PESQ). They also outperform the ITU-T Recommendation P.563 in estimating the effect that packet loss has on speech quality. The GP discovered models prove suited to real-time and in vivo evaluation of VoIP calls. Additionally, they are deployable on a wide variety of hardware platforms.

A new formalism for mathematical description and verification of component-based systems

In this paper, we introduce a formal approach for composing software components into a distributed system. We describe the system as a hierarchical composition of some components, which can be distributed on a wide variety of hardware platforms and executed in parallel. We represent each component by a mathematical model and specify the abstract communication protocols of the components using Interface Automata (IAs). To model hierarchical systems, besides the basic components' model, we will present other components, called nodes. A node consists of a set of subnodes interacting under the supervision of a controller. Each subnode, in turn, is a node or discrete event component. By considering a subnode as a node we can make hierarchical nodes/components. The entire system, therefore, forms the root of the hierarchy. A controller, in turn, is a set of subcontrollers/interface automata that specifies interaction protocol of the components inside a node. We have also presented an example demonstrating the model by illustrating nodes, subnodes, controllers, and subcontrollers. To address the state space explosion problem in system verification, we utilize the controller as a contract for independent analysis of the components and their interactions. Therefore, a node will not be analyzed directly; instead, we will analyze the controller.

Hardware platform design decisions in embedded systems

Designers of embedded systems can choose between a large variety of different hardware platforms. The question often arising is which hardware platform is suited best for a certain application. This decision is usually made by an expert in industry being familiar with a variety of hardware platforms. Therefore, it is of major interest how this expert knowledge and the skills necessary for such a selection process can be taught to students. In this paper a systematic hardware platform selection process based on hardware attributes is presented. Moreover, it is proposed how to integrate this approach in the embedded systems education.

Statistical Models for Empirical Search-Based Performance Tuning

Achieving peak performance from the computational kernels that dominate application performance often requires extensive machine-dependent tuning by hand. Automatic tuning systems have emerged in response, and they typically operate by (1) generating a large number of possible, reasonable implementations of a kernel, and (2) selecting the fastest implementation by a combination of heuristic modeling, heuristic pruning, and empirical search (i.e. actually running the code). This paper presents quantitative data that motivate the development of such a search-based system, using dense matrix multiply as a case study. The statistical distributions of performance within spaces of reasonable implementations, when observed on a variety of hardware platforms, lead us to pose and address two general problems which arise during the search process. First, we develop a heuristic for stopping an exhaustive compiletime search early if a near-optimal implementation is found. Secondly, we show how to construct run-time decision rules, based on run-time inputs, for selecting from among a subset of the best implementations when the space of inputs can be described by continuously varying features. We address both problems by using statistical modeling techniques that exploit the large amount of performance data collected during the search. We demonstrate these methods on actual performance data collected by the PHiPAC tuning system for dense matrix multiply. We close with a survey of recent projects that use or otherwise advocate an empirical search-based approach to code generation and algorithm selection, whether at the level of computational kernels, compiler and run-time systems, or problem-solving environments. Collectively, these efforts suggest a number of possible software architectures for constructing platform-adapted libraries and applications.

Comparative efficiencies of three parallel algorithms for nonlinear implicit transient dynamic analysis

The work reported in this paper is motivated by the need to develop portable parallel processing algorithms and codes which can run on a variety of hardware platforms without any modifications. The prime aim of the research work reported here is to test the portability of the parallel algorithms and also to study and understand the comparative efficiencies of three parallel algorithms developed for implicit time integration technique. The standard message passing interface (MPI) is used to develop parallel algorithms for computing nonlinear dynamic response of large structures employing implicit time-marching scheme. The parallel algorithms presented in this paper are developed under the broad framework of non-overlapped domain decomposition technique. Numerical studies indicate that the parallel algorithm devised employing the conventional form of Newmark time integration algorithm is faster than the predictor-corrector form. It is also accurate and highly adaptive to fine grain computations. The group implicit algorithm is found to be extremely superior in performance when compared to the other two parallel algorithms. This algorithm is better suited for large size problems on coarse grain environment as the resulting submeshes will obviously be large and thus permit larger time steps without losing accuracy.