Variable Length Decoding Research Articles

Improved MPEG-4 high-efficiency AAC with variable-length soft-decision decoding of the quantized spectral coefficients

MPEG-4 High-Efficiency Advanced Audio Coding (HE-AAC) is designed for low bit rate applications, such as audio streaming in mobile communications. The HE-AAC audio codec offers a better coding efficiency since variable-length codes (VLCs) are adopted. However, HE-AAC has originally been designed for storage and error-free transmission conditions. For the transmission over bit error-prone channels, error propagation is a serious problem for the VLCs. Therefore, a robust HE-AAC decoder is desired, especially for mobile communications. In contrast to traditional hard-decision decoding, utilizing bit-wise channel reliability information, soft-decision (SD) decoding has been known to offer better audio quality. In HE-AAC, the global gain parameter is coded with fixed-length codes (FLCs), while the scale factors and quantized spectral coefficients are coded with VLCs. In this work, we apply FL/SD decoding to the global gain parameter, VL/SD decoding to the parameters scale factors and quantized spectral coefficients. Especially, in order to apply VL/SD decoding to the quantized spectral coefficients, a new modified trellis representation in VL/SD decoding is proposed. An improved HE-AAC performance is clearly observed, with the support of both instrumental measurements and a subjective listening test.

Memory-efficient table look-up optimized algorithm for context-based adaptive variable length decoding in H.264/advanced video coding

Table look-up operation plays a very important role during the decoding processing of context-based adaptive variable length decoding (CAVLD) in H.264/advanced video coding (AVC). However, frequent table look-up operation can result in big table memory access, and then lead to high table power consumption. Aiming to solve the problem of big table memory access of current methods, and then reduce high power consumption, a memory-efficient table look-up optimized algorithm is presented for CAVLD. The contribution of this paper lies that index search technology is introduced to reduce big memory access for table look-up, and then reduce high table power consumption. Specifically, in our schemes, we use index search technology to reduce memory access by reducing the searching and matching operations for code_word on the basis of taking advantage of the internal relationship among length of zero in code_prefix, value of code_suffix and code_lengh, thus saving the power consumption of table look-up. The experimental results show that our proposed table look-up algorithm based on index search can lower about 60% memory access consumption compared with table look-up by sequential search scheme, and then save much power consumption for CAVLD in H.264/AVC.

Fast CAVLD of H.264/AVC on bitstream decoding processor

Abstract This paper presents a fast context-based adaptive variable-length decoding (CAVLD) method of H.264/AVC with a very long instruction word-based bitstream processing unit (BsPU) designed for entropy decoding of multiple video formats. A new table mapping algorithm for the coeff_token, level, and run_before syntax elements of the quantized transform coefficients is proposed, and many branch operations are removed by utilizing several designated instructions in the BsPU. By applying designated instructions and the proposed table mapping algorithm to CAVLD, we found that the proposed fast CAVLD method achieves an increase of approximately 47% in the decoding speed and a reduction of approximately 59% in memory requirements for the table mapping.

Context Adaptive Variable Length Decoding Optimization and Implementation on Tms320c64 Dsp for H.264/Avc

Context Adaptive Variable Length Decoding (CAVLD) module takes the lion chair of the H.264/AVC video decoder time due to its complexity. In order to ameliorate decoding speed, a new CAVLD algorithm and an efficient internal memory design were implemented on Digital Signal Processor (DSP). The proposed CAVLD algorithm, Zero Length Prefix (ZLP), was designed to optimize the first syntax element: the CoeffToken. ZLP implementation reduces CAVLD execution time to 21% instead of 41% from decoding time with a throughput of 1.28 MegaMB/s. In addition, the decoder speed was increased from 36 frames per second (fps) to 44 fps for a CIF compressed bitstream.

Fast thumbnail generation for MPEG video by using a multiple-symbol lookup table

A novel method using a multiple-symbol lookup table (mLUT) is proposed to fast-skip the ac coefficients (codewords) not needed to construct a dc image from MPEG-1/2 video streams, resulting in fast thumbnail generation. For MPEG-1/2 video streams, thumbnail generation schemes usually extract dc images directly in a compressed domain where a dc image is constructed using a dc coefficient and a few ac coefficients from among the discrete cosine transform (DCT) coefficients. However, it is required that all codewords for DCT coefficients should be fully decoded whether they are needed or not in generating a dc image, since the bit length of a codeword coded with variable-length coding (VLC) cannot be determined until the previous VLC codeword has been decoded. Thus, a method using a mLUT designed for fast-skipping unnecessary DCT coefficients to construct a dc image is proposed, resulting in a significantly reduced number of table lookups (LUT count) for variable-length decoding of codewords. Experimental results show that the proposed method significantly improves the performance by reducing the LUT count by 50%.

FPGA-oriented HW/SW implementation of the MPEG-4 video decoder

This paper presents an FPGA-oriented implementation methodology for the MPEG-4 video decoder based on a hardware/software co-design approach. The MPEG-4 decoder is based on MoMuSys optimized reference software combined with new hardware VLSI architectures. New architectures for input demultiplexing, variable length decoding and inverse discrete cosine transform are developed. All software and hardware structures are evaluated in terms of visual quality, computational complexity and memory bandwidth metrics. The presented implementation is compared with an optimized reference software-based solution. Simulation results demonstrate a reduction of decoder complexity, especially speed and memory bandwidth, while maintaining an acceptable quality of decoded sequences. The proposed hardware additions provide 30% speed improvement over software solution, thereby reducing the clock rate required to process full-rate video from 300 MHz down to 213 MHz. The MPEG-4 decoder was functionally tested on a Flextronics FPGA prototyping board.

Multiple-symbol parallel decoding for variable length codes

In this paper, a multiple-symbol parallel variable length decoding (VLD) scheme is introduced. The scheme is capable of decoding all the codewords in an N-bit block of encoded input data stream. The proposed method partially breaks the recursive dependency related to the VLD. First, all possible codewords in the block are detected in parallel and lengths are returned. The procedure results redundant number of codeword lengths from which incorrect values are removed by recursive selection. Next, the index for each symbol corresponding the detected codeword is generated from the length determining the page and the partial codeword defining the offset in symbol table. The symbol lookup can be performed independently from symbol table. Finally, the sum of the valid codeword lengths is provided to an external shifter aligning the encoded input stream for a new decoding cycle. In order to prove feasibility and determine the limiting factors of our proposal, the variable length decoder has been implemented on an field-programmable gate-array (FPGA) technology. When applied to MPEG-2 standard benchmark scenes, on average 4.8 codewords are decoded per cycle resulting in the throughput of 106 million symbols per second.

The use of intelligent data analysis techniques for system-level design: a software estimation example

System-level designers typically rely on white-box detailed descriptions of embedded systems in order to perform their design choices and optimisations. The white-box approach assumes that the complexity of the system can be managed by decomposing the global system into a set of simple and well-described components. This assumption is generally not true when non-linear interactions happen between the different subsystems. This paper explores, as an alternative, a black-box modelling methodology based on intelligent data analysis in order to support system-level designers in characterising the performance of embedded applications. The rationale behind this approach is that nowadays the designer can easily store large amount of data related to the system, and consequently discover relevant information by analysing them in a black-box fashion. As a case study, we address the performance modelling of software applications running on an embedded microprocessor. We introduce a data analysis method which, on the basis of a high-level characterisation of the software functionality and the hardware architecture, is able to predict the number of execution cycles on a embedded processor. We propose the adoption of a local learning technique (lazy learning), which proved already to be effective in previous works, to model the unknown input/output relation between the hardware/software parameters of the application and the number of execution cycles. Experiments with standard computational code (sorting, mathematical computation) and with a specific streaming algorithm for MPEG variable length decoding are presented to support this claim.

ＶＬＩＷ型メディアプロセッサを用いたＭＰＥＧ‐２オールフォーマットビデオデコーダ

An all-format decoder (AFD), which is an MPEG-2 MP@HL video decoder, has been developed for digital television. It uses a media accelerated processor for consumer appliances 2000 (MAPCA2000), which is based on the very-long-instruction-word architecture. The AFD decodes an MPEG-2 video stream using some of the discrete cosine transform coefficients in the input stream. The algorithm it uses to decode the stream reduces the amount of memory and processor power required. By efficiently using single-instruction multiple-data instructions, a direct-memory-access engine, and a co-processor for variable-length decoding, the AFD can decode 1080i-format video streams in real time using a standard MAPCA2000 running on a 300-MHz CPU with a 100-MHz external-memory bus clock and only 3.5 MB of external memory.

A low power variable length decoder for MPEG-2 based on nonuniform fine-grain table partitioning

Variable length coding is a widely used technique in digital video compression systems. Previous work related to variable length decoders (VLDs) was primarily aimed at high throughput applications, but the increased demand for portable multimedia systems has made power a very important factor. In this paper, a data-driven variable length decoding architecture is presented, which exploits the signal statistics of variable length codes to reduce power. The approach uses fine-grain lookup table (LUT) partitioning to reduce switched capacitance based on codeword frequency. The complete VLD for MPEG-2 has been fabricated and consumes 530 /spl mu/W at 1.35 V with a video rate of 48-M discrete cosine transform samples/s using a 0.6-/spl mu/m CMOS technology. More than an order of magnitude power reduction is demonstrated without performance loss compared to a conventional parallel decoding scheme with a single LUT.

Single chip dual-issue risc processor for real-time MPEG-2 software decoding

A single chip system for real–time MPEG–2 decoding can be created by integrating a general purpose dual–issue RISC processor, with a small dedicated hardware for the variable length decoding (VLD) and block loading processes; a 32KB instruction RAM; and a 32KB data RAM. The VLD hardware performs Huffman decoding on the input data. The block loader performs the half–sample prediction for motion compensation and acts as a direct memory access (DMA) controller for the RISC processor by transferring data between an external 2MB DRAM and the internall 32 KB data RAM. The dual-issue RISC processor, running at 250MHz, is enhanced with a set of key sub-word and multimedia instructions for a sustained peak performance of 1000 MOPS. With this setup for MPEG-2 decoding applications, bi-directionally predicted non-intra video blocks are decoded in less than 800 cycles, leading to a single-chip, real-time MPEG-2 decoding system.

Single Chip Dual---Issue RISC Processor for Real---Time MPEG---2 Software Decoding

A single chip system for real–time MPEG–2 decoding can be created by integrating a general purpose dual–issue RISC processor, with a small dedicated hardware for the variable length decoding (VLD) and block loading processes; a 32KB instruction RAM; and a 32KB data RAM. The VLD hardware performs Huffman decoding on the input data. The block loader performs the half–sample prediction for motion compensation and acts as a direct memory access (DMA) controller for the RISC processor by transferring data between an external 2MB DRAM and the internall 32 KB data RAM. The dual-issue RISC processor, running at 250MHz, is enhanced with a set of key sub-word and multimedia instructions for a sustained peak performance of 1000 MOPS. With this setup for MPEG-2 decoding applications, bi-directionally predicted non-intra video blocks are decoded in less than 800 cycles, leading to a single-chip, real-time MPEG-2 decoding system.