Variable-gain Power Amplifier Research Articles

A 39-GHz Phase-Inverting Variable Gain Power Amplifier in 65-nm CMOS for 5G Communication

This letter presents a 39-GHz phase-inverting variable gain power amplifier (VGPA) for 5G communication. Adopting a Gilbert structure-based variable gain amplifier (VGA) stage, the VGPA realized the dB-linear gain control characteristic as well as 180° phase inversion. At 0°/180° phase states, the 39-GHz VGPA achieves the maximum gain of 38.7/38.9 dB with gain tuning range of 5.6/5.2 dB, respectively. Over 38–43 GHz, the phase inversion error is limited within 5.9°, and the rms phase error is less than 3.6°/2.2°. Meanwhile, with the metal interleaving coplanar transformer matching network, this VGPA achieves 17.7/17.6-dBm Psat and 13.2/13.36-dBm OP1 dB, with the power added efficiency (PAE) of 35%/34.5% and 13.6%/14.4% at the saturation and 1-dB compression points, respectively. Over the gain control states, the OP1 dB fluctuation is less than 0.3 dB. Implemented in a 65-nm CMOS process, the proposed VGPA consumes 150 mW with a chip area of 0.3 mm2.

Optimizing RF Efficiency of a Vector-Modulator-Driven Antenna Array

The feed vector of an antenna array determines the array pattern and the active input impedance of each element. On the other hand, the output impedance of a variable-gain power amplifier, such as that used in a vector-modulator, depends on the amplification level. The resulting impedance mismatch is typically neglected when designing and controlling antenna arrays at the cost of reduced gain, bandwidth, and beam-steering range. This letter presents a simple method to find the array feed vector that maximizes the realized gain in a given direction in a case when the power amplifier output impedance depends on its amplification level. We verify the method with simulations for a test case consisting of a 4×1 patch array fed with ideal phase-shifters and realistic amplifiers. The simulation results of the case study show that the method improves transmission efficiency by $\text{3.5 dB}$ on average compared to the traditional phase shift.

A Multiband, Spectrally-Efficient Impulse Radio Transmitter Design with Low-Complexity CMOS Pulse Generator for IEEE 802.15.4a Application

A novel multiband impulse radio ultra-wideband (MB-IR-UWB) transmitter with an energy-efficient and low-complexity pulse generator design technique compliant with the IEEE 802.15.4a standard is investigated in this paper. This transmitter is made up of a new differential narrow triangular pulse generator, a new multiband voltage-controlled oscillator (VCO), an active mixer and a variable-gain power amplifier (PA). It operates at 14 UWB bands and generates an output signal with the duration of 3[Formula: see text]ns, more than 500[Formula: see text]MHz of channel bandwidth and more than 20[Formula: see text]dB of sidelobe suppression, while achieving an average energy efficiency of 51.36 pJ/pulse from 1.4-V supply. Improving spectral flexibility and worldwide compliance is the major contribution brought by this paper to make this circuit as a multifunction wireless device well suited for low-cost, low-power multiband applications.

A monolithic 3.1–4.8 GHz MB-OFDM UWB transceiver in 0.18-μm CMOS

A monolithic RF transceiver for an MB-OFDM UWB system in 3.1–4.8 GHz is presented. The transceiver adopts direct-conversion architecture and integrates all building blocks including a gain controllable wideband LNA, a I/Q merged quadrature mixer, a fifth-order Gm–C bi-quad Chebyshev LPF/VGA, a fast-settling frequency synthesizer with a poly-phase filter, a linear broadband up-conversion quadrature modulator, an active D2S converter and a variable-gain power amplifier. The ESD protected transceiver is fabricated in Jazz Semiconductor's 0.18-μm RF CMOS with an area of 6.1 mm2 and draws a total current of 221 mA from 1.8-V supply. The receiver achieves a maximum voltage gain of 68 dB with a control range of 42 dB in 6 dB/step, noise figures of 5.5–8.8 dB for three sub-bands, and an in-band/out-band IIP3 better than −4 dBm/+9 dBm. The transmitter achieves an output power ranging from −10.7 to −3 dBm with gain control, an output P1dB better than −7.7 dBm, a sideband rejection about 32.4 dBc, and LO suppression of 31.1 dBc. The hopping time among sub-bands is less than 2.05 ns.

Variable-gain power amplifier for mobile WCDMA applications

A single-chip linear power amplifier (PA) with >48-dB gain control range and >24-dBm output power with adjacent channel leakage power below -36 dBc is presented. The chip is realized using an AlGaAs-GaAs heterojunction-bipolar-transistor process and is aimed for 1.95-GHz mobile WCDMA applications. The amplifier consists of two blocks, the variable-gain amplifier, and the PA. The chip size is 1.3/spl times/1.1 mm/sup 2/ and it is mounted on an 8/spl times/8 mm/sup 2/ FR-4 type laminate with 26 pieces of 0402 surface-mountable discrete components composing a complete 50-/spl Omega/ input-output amplifier module. This paper presents the design of the two blocks, discusses issues related to their combination, and presents complete amplifier realization and measurement results.