Variable Gain Amplifier Circuit Research Articles

Layout Automation of Variable Gain Amplifier Circuit based on TCL Language

Layout Automation of Variable Gain Amplifier Circuit based on TCL Language

A Wideband dB-Linear VGA With Temperature Compensation and Active Load

In this paper, a wideband accurate dB-linear variable-gain amplifier (VGA) is presented, which consists of three cascading gain stages with dc-offset cancellation. Based on duplicate biasing and active load techniques, this VGA achieves merits such as simple and accurate continuous dB-linear gain control, gain robustness to process and supply voltage variation and constant bandwidth at different gain settings. The dB-linear gain control is realized based on exponential current steering. The exponential conversion can be based on bipolar transistors or MOS transistors in subthreshold region. Both ways are implemented in this design for comparison purpose. With temperature compensation circuit, this VGA is insensitive to temperature variation. All gain stages of the VGA share the same biasing, exponential V-I conversion and temperature compensation circuits to reduce design complexity. This proposed VGA is fabricated in 55-nm CMOS technology with a core area of 0.033 mm2. The measurement results show the proposed VGA has a dB-linear gain-control range from −37dB to 14 dB with an error within 0.65 dB. The −3dB bandwidth of the VGA is 740 MHz and is nearly constant when the gain varies. The core VGA circuit consumes about 2.49 mW. The proposed design features wide bandwidth, small chip area, and low power consumption.

Low power CMOS variable gain amplifier design for a multistandard receiver WLAN/WIMAX/LTE

This paper deals with a new compact low-power variable gain amplifier (VGA) architecture design for wireless communication multistandard receivers. The proposed VGA is a two stages cascaded topology that includes a folded cascode operational transconductance amplifier stage and a VGA core. The new “cell” structure has been introduced to demonstrate the performance enhancement with the use of only one VGA stage. The heuristic method is used to optimize the proposed circuit performance for high gain, low noise and low power consumption. This circuit is implemented and simulated using device-level description of TSMC 0.18 µm CMOS process. The simulation results indicate that the new VGA achieves a gain ranging from a minimum of − 25 dB toa maximum reaching 79 dB with a large bandwidth of 200 MHz. The designed VGA circuit acquires a noise figure less than 18 dB, an input referred noise of around 9.3 nV2/Hz and the third order intercept point measured at the input (IIP3) of 15 dBm. The proposed circuit consumes only 0.5 mW under 1.8 V supply voltage.

A new current mode CMOS variable gain amplifier using a new pseudo-exponential function

In this paper, a new pseudo-exponential function is described and a new CMOS exponential-control variable gain amplifier (VGA) based on the new function is introduced. No multiplier is needed in the proposed approach. The VGA operates in current mode and includes two different stages. The first stage is a simple current amplifier while the second stage is an attenuator. The overall behavior of the stages gives the new pseudo-exponential function. The VGA circuit has been designed and simulated for a 0.18 μ CMOS process. Post layout results show that the circuit has a bandwidth of 164 MHz and a gain range of 32.5 dB between − 21 and + 11.5 dB.

CDS Circuit with High-Performance VGA Functionality and Its Design Procedure

In order to process charge-coupled-device (CCD) signals, a correlated double sampling (CDS) circuit is necessary for noise elimination. Furthermore, in order to amplify the CCD signals to proper amplitude, an extra variable-gain amplifier (VGA) circuit is also necessary for providing gain. In traditional works, for conciseness and efficiency, those separated CDS and VGA circuits are combined together into a single circuit. However, such a CDS circuit with embedded VGA can provide only several different gain values and 12-bit sampling resolution at most, which cannot meet the increasing demands from the users. Hence, for this reason, a new CDS circuit with embedded VGA has been proposed in this paper. This new CDS circuit has five advantages: high resolution of VGA-gain programming (512 different gain values), wide span of VGA-gain range (0---18 dB), good linearity of VGA-gain curve (linear-in-dB), fast sampling rate (80 MHz), and high sampling resolution (14-bit). Furthermore, this new CDS circuit can automatically convert "single-ended input signal" into "dual-ended output signal," facilitating subsequent signal processing. Finally, this proposed circuit is fabricated in SMIC 0.18 $$\upmu \hbox {m}$$μm 3.3 V CMOS process. Under 80 MHz sampling rate, the measurement results show that the SNR is 72.96 dB; the SFDR is 80 dB; and the ENOB is 11.54-bit.

A Single-Stage 37 dB-Linear Digitally-Controlled Variable Gain Amplifier for Ultrasound Medical Imaging

This paper presents a variable gain amplifier (VGA) for an analog front-end (AFE) of ultrasound medical imaging. This VGA has a closedloop topology and shows a 37-dB-linear characteristic with a single-stage amplifier. It consists of an op-amp, a non-binary-weighted capacitor array, and a gaincontrol block. This non-binary-weighted capacitor array reduces the required number of capacitors and the complexity of the gain-control block. The VGA has been fabricated in a 0.35-mm CMOS process. This work gives the largest gain range of 37 dB per stage, the largest P1 dB of 9.5 dBm at the 3.3-V among the recent VGA circuits available in the literature. The voltage gain is controlled in the range of [-10, 27] dB in a linear-in-dB scale with 16 steps by a 4-bit digital code. The VGA has a bandpass characteristic with a passband of [20 kHz, 8 MHz].

HIGH LINEARITY CMOS VARIABLE GAIN AMPLIFIER FOR UWB APPLICATIONS

A large dynamic-range Variable Gain Amplifier (VGA) suitable for Ultra Wide Band (UWB) applications is presented. The VGA is composed of three programmable variable gain amplifier stages followed by an output buffer. Such wide bandwidth allows our proposed VGA to be used in multi-standard protocols. Power reduction is developed for the variable gain amplifier stages. Thorough analyses of the mid-band gain and noise are presented; and design tradeoffs are carefully handled. The VGA circuit is designed and simulated in 0.13 μm IBM-CMOS process; the overall VGA with buffer consumes 25 mA from a 1.5 V supply. The VGA achieves 54.5 dB dynamic-range (DR), 17.6 dBm IIP3, -42.31 dB THD at peak-to-peak differential output voltage of 1 V, and frequency 400 MHz. Moreover; the proposed circuit reports a good noise performance; the average integrated noise is 121.6 nV/Hz at minimum gain of -0.5 dB.

Multi-channel Waveform Sampling ASIC for radiation detection and measurement

Abstract We have designed and fabricated a 16-channel Waveform Sampling ASIC for radiation detection and measurement. Waveform sampling is very important for the pulse shape analysis and discrimination, which is often used in radiation detection to discriminate different radiations such as alpha, beta and gamma rays. One channel of the fabricated ASIC consists of a charge-sensitive preamplifier, a VGA (Variable Gain Amplifier), an ADC (Analog to Digital Converter) and digital circuits. The preamplifier converts the current signal to the voltage signal, and the VGA amplifies the signal to appropriate level for the ADC. The ADC was designed to digitize the waveform with a frequency of 100 MHz and a resolution of 6bits. Digital circuits consist of a free-running ADC and a multiplexer which were designed to convert a digitized 100 MHz/6bit signal to a 200 MHz/3bit one, which is effective for the reduction of the number and for the achievement of the high integration in one chip. This chip was designed and fabricated with 0.35 μm CMOS technology by ROHM and the size of the ASIC is 4.9 mm by 4.9 mm. The design concept and some experimental results are shown in this paper.

A low power 48-dB/stage linear-in-dB variable gain amplifier for direct-conversion receivers

In this paper, a low power Variable Gain Amplifier (VGA) circuit with an approximation to exponential gain characteristic is presented. It is achieved using current mirrors to generate appropriate current signals to bias the input stage of the VGA circuit working in triode region, and the output stage working in saturation region, respectively. The VGA circuit presented herein comes with a 549μW maximum power consumption given a 1.8V supply. Most important of all, it has a linear-in-dB 48-dB dynamic gain range per stage. The effect of the input trasconductance and the output resistance on the linearity of gain control is also discussed. This circuit is fabricated using a 0.18μm standard CMOS process with a core area of 0.0045mm2.

Low-power and high-performance Automatic Gain Control systems based on nanoscale Field Effect Diode and SOI-MOSFET

The Automatic Gain Control (AGC) systems based on nanoscale Field Effect Diode (FED) and double gate silicon on insulator (SOI) MOSFET are investigated in this paper. Using double gate devices leads to more flexibility in gain controlling, improving performance, and power consumption reduction. Simulation results show these systems have better characteristics in terms of power and band-width in comparison with AGC system based on regular MOSFET. Among proposed alternative structures (SOI-MOS, MOSFET, FED), nanoscale FED is specifically suited for variable gain amplifier circuits in AGC systems which leads to improve performance and reduce power consumption in low-power applications. © IEICE 2010.

A Differential-Ramp Based 65 dB-Linear VGA Technique in 65 nm CMOS

In this paper, a differential-ramp based variable gain amplifier (VGA) technique is introduced. Using the proposed technique, digitally programmable gain amplifiers (PGAs) can be converted to analog controlled, dB-linear VGAs with minimum impact on noise and linearity. This provides an efficient way of realizing an analog controlled VGA for OFDM based applications. The technique is illustrated by converting an opamp based high-linearity, low-noise PGA to a dB-linear VGA for CMOS mobile TV applications. The design including the cascade of a two-stage continuous 65-dB-linear VGA and a third-order Sallen-Key buffer stage is fabricated in a 65 nm CMOS process. The measured in-band OIP3 of the whole chain at maximum gain of 47 dB is 22 dBm, whereas the blockers in the adjacent channel result in 34 dBm OIP3 for the same gain setting. The design achieves 11 nV/?(Hz) input referred noise density and occupies a die area of 0.17 mm2. The VGA circuit consumes 1.5 mA of current from a 1.2 V supply with an additional 200 ?A switch control ramp current from a 2.5 V supply.

A High Efficiency Variable Gain Amplifier Circuit with Controllable Transconductance Amp

A novel power reduction technique for a variable gain amplifier (VGA) with a two-stage operational amplifier is proposed. The technique improves the power consumption of a VGA by optimizing the bandwidth and the phase margin dynamically on all gain range of the VGA through controlling the input transconductance of opamp. A VGA utilizing the proposed technique shows 40% reduction of power consumption against a conventional VGA at the best condition of VGA gain range.

A CMOS Norton amplifier-based digitally controlled VGA for low-power wireless applications

A CMOS variable-gain amplifier (VGA) for use in the baseband section of integrated wireless receivers is presented. The VGA circuit is based on a new CMOS realization of the Norton transresistance amplifier. The proposed CMOS realization operates from a 3-V supply voltage with rail-to-rail swing and class AB input and output stages. The standby current of the class AB stages employed can be accurately controlled, leading to a low power consumption, nonslew-rate-limited response. The VGA circuit provides a precise process-independent gain control range of 30 dB with 1-dB gain step. The circuit uses current division techniques to provide an area-efficient 6-bit digital offset trimming capability. Experimental results from a test chip fabricated through MOSIS are provided.

Digitally programmable decibel-linear CMOS VGA for low-power mixed-signal applications

A new technique for realizing CMOS digitally-controlled decibel-linear variable gain amplifier (VGA) circuits is described. CMOS VGA circuits employing the proposed technique are then given. Besides being effective and simple to use from a system point of view, the VGA circuits offer a stable gain characteristic with precise gain control that is achievable without component spreading. The VGA provides a 25 dB gain control range per stage, with 0.55 dB gain steps and a gain error of less than 0.5 dB. It can also be digitally reconfigured to give a 60 dB gain control range with 6 dB gain steps. The VGA circuit provides digital offset trimming, processes voltage or current input signals and operates in a fully differential configuration. Simulation and experimental results are provided.

Digitally controlled dB-linear CMOS variable gain amplifier

A novel technique to implement a digitally controlled precise dB-linear variable gain amplifier (VGA) in CMOS technology is proposed. The technique is used to realise a robust low power CMOS VGA circuit without component spread. Experimental results from a 1.2 /spl mu/m CMOS chip are provided.

Gate-controlled lateral PNP BJT: characteristics, modeling and circuit applications

This paper describes the electrical characteristics, modeling and some circuit applications of a gate-controlled lateral pnp transistor (GC-LPNP) which has four electrodes-collector (C), base (B), emitter (E) and gate (G), and was fabricated using a 0.8 /spl mu/m BiCMOS technology. This device is composed of a surface PMOS FET and a bulk lateral pnp BJT in parallel, and it has unique dc characteristics of either variable current gain /spl beta//sub F/ of 10/sup 2//spl sim/10/sup 4/ for V/sub G/ variations from 0.4 to -0.4 V at V/sub E/ biases of 0.4 to 0.6 V, or variable transconductance g/sub M/ that increases by 3/spl sim/10 times as V/sub E/ increases from 0.4 to 0.7 V at V/sub G/ biases of -0.2 to -0.4 V. A circuit model of this new device, which is suitable for SPICE circuit simulation is proposed, and this model gives good agreement to the measured current-voltage curves over a wide range of V/sub C/-, V/sub E/- and V/sub G/-variations. Using this new four-electrode hybrid device, some special functional analog circuits, such as a variable-gain amplifier (VGA) and a mixer circuit, can be built very easily and exhibit good performance, For the VGA circuit, variations of the ac gain control of 0.4/spl sim/5.5 times for /spl delta/V/sub G/ varies over 1 V was obtained; and for the mixer, a conversion gain of 5 dB to 12 dB for input RF signal up to 400 MHz was obtained. PSPICE simulation results for the VGA circuit using the GC-LPNP device model are in good agreement with measurements. Finally, this new device which was fabricated using a typical BiCMOS technology, can be directly integrated with other digital/analog VLSI circuits for very attractive system applications, such as portable wireless communication systems.

A low-power CMOS VGA for 50 Mb/s disk drive read channels

We describe an all CMOS variable gain amplifier (VGA) suitable for use in disk drive read channels. The VGA maintains a 3 dB bandwidth greater than 85 MHz throughout its gain range. This ensures good phase linearity for data transfer rates of up to 50 Mb/s. The VGA provides a 25 db gain variation along an ideal exponential gain to control voltage curve and 30 dB of gain control if ideal exponential characteristics is not absolutely necessary. The VGA achieves the necessary exponential gain to control voltage characteristics intrinsically using only MOS transistors as a single unit to reduce power and area consumption. Overall power consumption is less than 10 mW for the VGA circuit excluding the off-chip buffer circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>