Use Of Systolic Arrays Research Articles

An Efficient CGM-Based Parallel Algorithm Solving the Matrix Chain Ordering Problem

This study focuses on the parallel resolution of the matrix chain ordering problem and the optimal convex polygon triangulation problem on the Coarse grain multicomputer model (CGM for short). There has been intensive work on the parallelization of these dynamic programming problems in PRAM, including the use of systolic arrays, but a BSP/CGM solution is necessary for ease of implementation and portability. Our CGM algorithm is based on Yao's sequential solution running in O(n2) time and O(n2) space. This CGM algorithm uses p processors, each with O(n/p) local memory. It requires at most O(S/p×n2) running time with S communication rounds and with S/p<1. Our algorithm performs better than the algorithm proposed in 2012 by Dilson and Marco when S is less than n/p. We offer several ways of partitioning the problem to solve and study the impact of each partitioning algorithm performance. A CGM solution exists based on Yao's algorithm, but the subdivision of tasks is defined according to the BSP cost model. In this paper, we propose a solution based only on the CGM model specifications. Note that S is the number of super-steps of the CGM algorithm.

Fast implementation of direct robot kinematics with cordic systolic arrays

This paper deals with fast implementation of the direct kinematics equations of robotic manipulators, using systolic arrays that incorporate one CORDIC rotor in their processing elements. The rotation or the translation motions of the links are implemented by using a processing element of general form. The processing elements used for the revolute joints incorporate one CORDIC rotor and at most an adder and one inverter. The processing elements used for the prismatic joints incorporate at most two adders and one inverter. The overall systolic architecture is derived by cascading the processing elements that correspond to the successive links and pipelining the unidirectional linear array. The use of systolic arrays with CORDIC processors results into fast pipelined VLSI architectures, which may be used as peripheral devices to a host digital computer and are suitable for computation of the kinematic equations, in run-time operation.

An example of a new VLSI design style based on systolic macrocells: A high‐speed single‐chip transversal filter for signal processing applications

AbstractThis paper describes the VLSI design of a high‐speed single‐chip FIR filter for data with a limited number of bits. A new design style that allows easy design of high speed VLSI systems was used. This style is based on the extensive use of systolic arrays and it is well suited to VLSI system realizations for digital signal processing (DSP) applications. This realization shows that high performance systems can be obtained with a systolic approach, using a few main building blocks called macrocells, systolic at the bit‐level, of general use and easily interconnected.

A fast high-performance array processing technique for angle-of-arrival estimation and detection of the number of incident signals

A new projection-based algorithm is proposed for estimating the angles of arrival of plane waves incident onto arrays of sensors. The method is based on a single <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">QR</i> decomposition of the signal covariance matrix; hence, it is much faster than eigen-based methods, which require many <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">QR</i> decompositions. It is shown that optimum performance is attained only if the columns of the covariance matrix are permuted in a prescribed manner before the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">QR</i> decomposition proceeds. An adjunct to the angle-of-arrival estimation process is a new eigenvalue-free technique for estimating the number of incident signals. The performance penalty associated with these new methods is insignificant. The real-time performance of this technique is enhanced through the use of systolic arrays. A novel systolic array structure is proposed for extracting both the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> matrices generated by the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">QR</i> decomposition.

Real-time systolic array processor for 2-D spatial filtering

The use of systolic arrays (SA) to implement two-D local state-space (LSS) digital filters for real-time image processing is presented. The simple modular structure of the SA is ideal for VLSI implementation. The array used is composed of ROM/adder (or multiplier/adder) cells and is shown to be 100% efficient. The size of the array is equal to the overall size of the system matrix and is much smaller than arrays where the number of cells equals the number of image pixels. Still, this array is capable of processing a 512*512 image in less than 1/30 seconds allowed in real-time applications for second-order filters. The use of ROMs along with the inherent good performance of LSS filters under the effect of finite-length registers, makes this implementation desirable. The array is also far less expensive than other proposed real-time two-D digital filter implementations. >

Implementation of convolution and Fourier transforms using 1-bit systolic arrays

The use of systolic arrays of 1-bit cells to implement circular convolution and DFTs is described. The architecture is very well suited to VLSI implementation. It is shown that considerable simplification of the architecture is possible for real-valued DFTs.

Implementation of signal processing functions using 1-bit systolic arrays

The use of systolic arrays of 1-bit cells to implement a range of important signal processing functions is demonstrated. Two examples, a pipelined multiplier and a pipelined bit-slice transform circuit, are given. This approach has many important implications for silicon technology, and these are outlined briefly.