Use Of High-k Materials Research Articles

Performance Analysis and Comparison of Different High-K Materials Used as Gate Dielectrics in DH-TMSG MOSFET

Abstract: To overcome SCEs and provide better packing density and performance a device called Double Halo Triple Material Surround Gate MOSFET is introduced. The device is designed by the combination of gate engineering and channel engineering. The device uses a surround gate MOSFET with triple material gate employing gate material engineering which improves the gate transport efficiency by modifying electric field pattern and surface potential along channel, resulting in higher carrier transport efficiency and SCEs. To extend the use of CMOS technology beyond 14 nm node technology, new device materials are required that can enhance the performance of MOSFETs. The use of high-k materials in double gate (DG) MOSFET can triumph over the problem of power dissipation and leakage current. The further mitigation in device dimension becomes a challenging task due to the existence of unavoidable short channel effects. The introduction of gate stack and channel engineering in MOSFET devices open a new window for future generation devices. The gate dielectric materials have played a significant role in the design of novel and high performances at nanoscale of electrical devices. It can be observed that when approaching a higher value of dielectric constant, the on current increases while the subthreshold slope (SS) threshold voltage (Vth) and leakaga current reduced. The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large.

Structural characterization of tantalum nitride films as wet etch stop layer in advanced multiwork function metal gate MOSFETs

As the dimensions of semiconductor devices become smaller, the use of high-k materials as gate oxides has become necessary for controlling gate leakage current. In addition, to achieve higher performance, conventional polysilicon metal gates have been replaced with multistack metal electrodes with engineered work functions. Thus, a suite of devices with different levels of performance and power usage is available. The integration scheme to create such structures involves an additional deposition step and selective wet etching of titanium nitride (TiN) in a complex patterning scheme following the high-k film deposition. Tantalum nitride (TaN) is one of the candidates used as an etch stop layer in a bilayer scheme of TaN/TiN. This prevents any exposure of high-k hafnium oxide (HfO2) gate oxide to wet etch chemistry in the patterning scheme, which could cause damage and/or skimming, resulting in undesirable effects on device characteristics and reliability. In order to accommodate for shrinking trench widths, these bilayer stacks are kept as thin as possible, which makes monitoring the thickness during various patterning steps very challenging. In this study, the authors present an approach to an offline and inline metrology setup. In order to gain insight into basic layer growth and interdiffusion characteristics, they used x-ray photoelectron spectroscopy and high-resolution transmission electron microscopy. They utilized specular x-ray reflectivity as a first principles method, followed by wavelength dispersive x-ray fluorescence to gain insight into cross-wafer variation on blanket wafers. The results were then fed into models developed for the x-ray photoelectron spectroscopy technique, which can be used as an inline method to characterize the composition and thickness of the patterned wafers for both as-deposited and postetching.

Simulation study of HEMT structures with HfO2 cap layer for mitigating inverse piezoelectric effect related device failures

The Inverse Piezoelectric Effect (IPE) is thought to contribute to possible device failure of GaN High Electron Mobility Transistors (HEMTs). Here we focus on a simulation study to probe the possible mitigation of the IPE by reducing the internal electric fields and related elastic energy through the use of high-k materials. Inclusion of a HfO2 “cap layer” above the AlGaN barrier particularly with a partial mesa structure is shown to have potential advantages. Simulations reveal even greater reductions in the internal electric fields by using “field plates” in concert with high-k oxides.

Ultra Thin Oxide by Chemical Vapour Oxidation of Si

Continued MOSFET scaling necessitates the use of high-k materials which in turn need an ultra thin (<0.6nm) SiO2 buffer layer between the high-k material and the silicon substrate, to obtain a better interface. In this paper a novel technique to grow extremely thin (as low as 0.6 nm) oxide by nitric acid vapour at low temperature and effect of ac anodization on these oxides are discussed. The effective oxide thickness obtained for these chemical oxides has been found to be ranging from 0.6 nm to 1.5 nm. C-V, I-V and reliability characteristics have been studied. The oxide thickness increases with increase in molarity of the HNO3. At an electric field of 10 MV/cm, the leakage current density for the thinnest oxide is 0.6 A/cm2. These values are better than those for oxides grown in HNO3 solution. Anodization improved the quality of the chemical vapour oxides further.

Thermally Grown and Reoxidized Nitrides as Alternative Gate Dielectrics

ABSTRACTThe use of high-k materials as gate dielectric still meets a lot of unsolved problems such as thermal instability during post deposition anneals resulting in the formation of interfacial oxide layers or bad process compatibility. As long as these requirements are not accomplished alternative gate dielectrics have to be formed by oxynitrides or gate stacks built of oxynitrides and some high-k material. In order to achieve a low equivalent oxide thickness (EOT) it is necessary to grow homogeneously thin oxynitrides which are nitrogen-rich and which have a high interface quality. Therefore we have studied the growth of thin nitrides and oxynitrides (EOT = 1 – 2nm) formed by rapid thermal nitridation in NH3 and wet reoxidation. By varying the partial pressure of NH3 in the process gas ambient NH3/Ar the nitride quality could be optimized: it was found that an optimized ratio of NH3 and Ar during nitridation improves the electrical properties of the nitrides and oxynitrides significantly. Interface state densities as low as those of dry thermal oxides and leakage current densities reduced by four orders of magnitude compared to SiO2 of the same EOT have been obtained. Due to the high incorporation of nitrogen into the oxynitride by rapid thermal nitridation and following oxidation the leakage current densities are also lower than those of most oxynitrides reported in literature. In addition we present data concerning the suppression of boron diffusion from p+ poly-Si electrodes. In summary the developed oxynitrides are suitable to bridge the gap between common SiO2 and new alternative gate dielectrics or to form gate stacks in combination with high-k materials.