Use Of Field-programmable Gate Array Resources Research Articles

Developing a Portable Fluorescence Imaging Device for Fish Freshness Detection.

Rapid detection of fish freshness is of vital importance to ensuring the safety of aquatic product consumption. Currently, the widely used optical detecting methods of fish freshness are faced with multiple challenges, including low detecting efficiency, high cost, large size and low integration of detecting equipment. This research aims to address these issues by developing a low-cost portable fluorescence imaging device for rapid fish freshness detection. The developed device employs ultraviolet-light-emitting diode (UV-LED) lamp beads (365 nm, 10 W) as excitation light sources, and a low-cost field programmable gate array (FPGA) board (model: ZYNQ XC7Z020) as the master control unit. The fluorescence images captured by a complementary metal oxide semiconductor (CMOS) camera are processed by the YOLOv4-Tiny model embedded in FPGA to obtain the ultimate results of fish freshness. The circuit for the YOLOv4-Tiny model is optimized to make full use of FPGA resources and to increase computing efficiency. The performance of the device is evaluated by using grass carp fillets as the research object. The average accuracy of freshness detection reaches up to 97.10%. Moreover, the detection time of below 1 s per sample and the overall power consumption of 47.1 W (including 42.4 W light source power consumption) indicate that the device has good real-time performance and low power consumption. The research provides a potential tool for fish freshness evaluation in a low-cost and rapid manner.

Emulator of a Boost Converter for Educational Purposes

Project-based learning (PBL) is proposed for the development of a Hardware-in-the-Loop (HIL) platform and the design of its digital controller for an undergraduate course on Digital Electronic Systems. The objective for students is the design of a digitally controlled HIL Boost converter, a digital pulse-width modulator (DPWM) and a current mode controller, implemented in field-programmable gate array (FPGA) devices. To this end, the different parts of the project are developed and evaluated, maximizing the use of FPGA resources in the design of the HIL and DPWM blocks, and applying design techniques that minimize the use of the digital resources used in the design of the controller. Students are equipped with a new individualized educational experience, allowing them to test their technical competence and knowledge in an environment close to the reality of the industry.

Efficient FPGA Implementation of Address Generator for WiMAX Deinterleaver

In this brief, a low-complexity and novel technique is proposed to efficiently implement the address generation circuitry of the 2-D deinterleaver used in the WiMAX transreceiver using the Xilinx field-programmable gate array (FPGA). The floor function associated with the implementation of the steps, required for the permutation of the incoming bit stream in channel interleaver/deinterleaver for IEEE 802.16e standard is very difficult to implement in FPGA. A simple algorithm along with its mathematical background developed in this brief, eliminates the requirement of floor function and thereby allows low-complexity FPGA implementation. The use of an internal multiplier of FPGA and the sharing of resources for quadrature phase-shift keying, 16-quadrature-amplitude modulation (QAM), and 64-QAM modulations along with all possible code rates makes our approach to be novel and highly efficient when compared with conventional look-up table-based approach. The proposed approach exhibits significant improvement in the use of FPGA resources. Exhaustive simulation has been carried out to claim supremacy of our proposed work.

Design Space Pruning Through Early Estimations of Area/Delay Tradeoffs for FPGA Implementations

Early performance feedback and design space exploration of complete field-programmable gate array (FPGA) designs are still time consuming tasks. This paper proposes an original methodology based on estimations to reduce the impact on design time. It promotes a hierarchical exploration to mitigate the complexity of the exploration process. Therefore, this work takes place before any design step, such as compilation or behavioral synthesis, where the specification is still provided as a C program. The goal is to provide early area and delay evaluations of many register-transfer level (RTL) implementations to prune the design space. Two main steps compose the flow: 1) a structural exploration step defines several RTL implementations, and 2) a physical mapping estimation step computes the mapping characteristics of these onto a given FPGA device. For the structural exploration, a simple yet realistic RTL model reduces the complexity and permits a fast definition of solutions. At this stage, it focuses on the computation parallelism and memory bandwidth. Advanced optimizations using for instance loop tiling, scalar replacement, or data layout are not considered. For the physical estimations, an analytical approach is used to provide fast and accurate area/delay tradeoffs. The paper also do not consider the impact of routing on critical paths or other optimizations. The reduction of the complexity allows the evaluation of key design alternatives, namely target device and parallelism that can also include the effect of resource allocation, bitwidth, or clock period. Due to this, a designer can quickly identify a reliable subset of solutions for which further refinement can be applied to enhance the relevance of the final architecture and reach a better use of FPGA resources, i.e., an optimal level of performance. Experiments performed with Xilinx (VirtexE) and Altera (Apex20K) FPGAs for a two-dimensional Discrete Wavelet Transform and a G722 speech coder lead to an average error of 10% for temporal values and 18% for area estimations