Use Of External Memory Research Articles

All-optical organic photochemical integrated nanophotonic memory: low-loss, continuously tunable, non-volatile

Controlling changes in the optical properties of photonic devices allows photonic integrated circuits (PICs) to perform useful functions, leading to a large breadth of applications in communications, computing, and sensing. Many mechanisms to change optical properties exist, but few allow doing so in a reversible, non-volatile manner. Without such mechanisms, power inefficiencies and use of external memory are inevitable. In this work, we propose and experimentally demonstrate reversible, non-volatile phase actuation of a silicon nitride PIC with thermally stable photochromic organic molecules vapor-deposited within a slot waveguide structure. The use of a high-core-index platform allows the photochemical phase actuation of a planar-resonator-based photonic memory unit, which enables positive and negative signal weighting and permits integrated spectroscopic analysis. We show properties of this all-optical memory for a silicon photonics platform, including low loss in the optical C-band, first-order photokinetics of the photoconversion, bidirectional scalable switching, and continuous tuning. Such features are critical for memories in analog applications such as quantum, microwave, and neuromorphic photonics, where bipolar weights, low loss, and precision are paramount. More generally, this work suggests that back-end-of-line-compatible vapor deposition of organic molecules into silicon photonic circuits is promising to introduce non-silicon-native functionality.

Trends in Remote User Authentication Based on Smart Card and External Memory

This research performs a literature survey of remote user authentication researches based on smart card and external memory. The main security confidence of smart card based schemes is temper-resistance property. Other reasons are small physical size, portability, convenience of non-volatile memory, and security provided by a single chip computer embedded in a plastic card. The most efficient schemes are those that used hash function or ECC. The high cost of the cards and readers and their deployment remains a burden to issuers or users. This is what motivates the use of external memory instead of smart card. But the problem of non-temper resistance property associated with external memory limited researches in that direction. There are also, absence of other activities that are essential in user authentication such as forgot/reset password and re-registration in case the external memory or smart card is stolen or lost in all the reviewed researches.

Memory-Efficient Deep Learning on a SpiNNaker 2 Prototype.

The memory requirement of deep learning algorithms is considered incompatible with the memory restriction of energy-efficient hardware. A low memory footprint can be achieved by pruning obsolete connections or reducing the precision of connection strengths after the network has been trained. Yet, these techniques are not applicable to the case when neural networks have to be trained directly on hardware due to the hard memory constraints. Deep Rewiring (DEEP R) is a training algorithm which continuously rewires the network while preserving very sparse connectivity all along the training procedure. We apply DEEP R to a deep neural network implementation on a prototype chip of the 2nd generation SpiNNaker system. The local memory of a single core on this chip is limited to 64 KB and a deep network architecture is trained entirely within this constraint without the use of external memory. Throughout training, the proportion of active connections is limited to 1.3%. On the handwritten digits dataset MNIST, this extremely sparse network achieves 96.6% classification accuracy at convergence. Utilizing the multi-processor feature of the SpiNNaker system, we found very good scaling in terms of computation time, per-core memory consumption, and energy constraints. When compared to a X86 CPU implementation, neural network training on the SpiNNaker 2 prototype improves power and energy consumption by two orders of magnitude.

EmMAW: computing minimal absent words in external memory.

The biological significance of minimal absent words has been investigated in genomes of organisms from all domains of life. For instance, three minimal absent words of the human genome were found in Ebola virus genomes. There exists an O(n) -time and O(n) -space algorithm for computing all minimal absent words of a sequence of length n on a fixed-sized alphabet based on suffix arrays. A standard implementation of this algorithm, when applied to a large sequence of length n , requires more than 20 n bytes of RAM. Such memory requirements are a significant hurdle to the computation of minimal absent words in large datasets. We present emMAW, the first external-memory algorithm for computing minimal absent words. A free open-source implementation of our algorithm is made available. This allows for computation of minimal absent words on far bigger data sets than was previously possible. Our implementation requires less than 3 h on a standard workstation to process the full human genome when as little as 1 GB of RAM is made available. We stress that our implementation, despite making use of external memory, is fast; indeed, even on relatively smaller datasets when enough RAM is available to hold all necessary data structures, it is less than two times slower than state-of-the-art internal-memory implementations. https://github.com/solonas13/maw (free software under the terms of the GNU GPL). alice.heliou@lix.polytechnique.fr or solon.pissis@kcl.ac.uk. Supplementary data are available at Bioinformatics online.

W-tree

World Wide Web applications need to use, constantly update, and maintain large webgraphs for executing several tasks, such as calculating the web impact factor, finding hubs and authorities, performing link analysis by webometrics tools, and ranking webpages by web search engines. Such webgraphs need to use a large amount of main memory, and, frequently, they do not completely fit in, even if compressed. Therefore, applications require the use of external memory. This article presents a new compact representation for webgraphs, called w-tree , which is designed specifically for external memory. It supports the execution of basic queries (e.g., full read, random read, and batch random read), set-oriented queries (e.g., superset, subset, equality, overlap, range, inlink, and co-inlink), and some advanced queries, such as edge reciprocal and hub and authority. Furthermore, a new layout tree designed specifically for webgraphs is also proposed, reducing the overall storage cost and allowing the random read query to be performed with an asymptotically faster runtime in the worst case. To validate the advantages of the w-tree, a series of experiments are performed to assess an implementation of the w-tree comparing it to a compact main memory representation. The results obtained show that w-tree is competitive in compression time and rate and in query time, which may execute several orders of magnitude faster for set-oriented queries than its competitors. The results provide empirical evidence that it is feasible to use a compact external memory representation for webgraphs in real applications, contradicting the previous assumptions made by several researchers.

Reconfigurable architecture for real-time image compression on-board satellites

Data products of optical remote sensing systems are increasingly used in many areas of our everyday life. The spatial as well as the spectral resolution of satellite image data increases steadily with new missions resulting in a higher precision of known procedures and new application scenarios. While the memory capacity requirements can still be fulfilled, the transmission capacity becomes increasingly problematic. Real-time transmission of high-resolution image data is currently not possible. This thesis presents a new image data compression architecture that can be used for current and future projects at the German Aerospace Center (DLR). The architecture has region-of-interest support and offers flexible access to the compressed data based on the CCSDS 122.0-B-1 image data compression standard. Region of interest (ROI) coding can be useful in scenarios where on-board classification, registration, or object or change detection algorithms are used. It is also useful to decrease the amount of data that must be transferred to the ground station. Modifications to the standard have been made to permit a change of compression parameters and the re-organization of the bit-stream after compression. An additional index of the compressed data is created, which makes it possible to locate individual parts of the bit-stream. On request, compressed and stored images can be re-assembled and transmitted according to the application's needs and as requested by the ground station. The requirements, the design of the architecture, and its implementation based on reconfigurable hardware are presented. The architecture was developed for a spacequalified Xilinx Virtex 5QV, where a single instance of the architecture is capable of compressing images at a rate of up to 200 Mpx/s (or 400 Mbyte/s for 16 bit images). It operates at a clock frequency of 100MHz and processes two image pixels per clock cycle. A Xilinx Virtex-5QV enables thereby compressing images with a width of up to 4096 pixels without the use of external memory. Without external memory and additional interfaces, the power consumption of the architecture is about 5 W. The proposed architecture is one of the fastest implementations yet reported and sufficient for recent high-resolution systems. Investigations in the resource and power consumption, as well as the availability of external storage have shown that it should be possible to integrate the design directly on a focal plane.

Lightweight algorithms for constructing and inverting the BWT of string collections

Recent progress in the field of DNA sequencing motivates us to consider the problem of computing the Burrows–Wheeler transform (BWT) of a collection of strings. A human genome sequencing experiment might yield a billion or more sequences, each 100 characters in length. Such a dataset can now be generated in just a few days on a single sequencing machine. Many algorithms and data structures for compression and indexing of text have the BWT at their heart, and it would be of great interest to explore their applications to sequence collections such as these. However, computing the BWT for 100 billion characters or more of data remains a computational challenge.In this work we address this obstacle by presenting a methodology for computing the BWT of a string collection in a lightweight fashion. A first implementation of our algorithm needs O(mlogm) bits of memory to process m strings, while a second variant makes additional use of external memory to achieve RAM usage that is constant with respect to m and negligible in size for a small alphabet such as DNA. The algorithms work on any number of strings and any size. We evaluate our algorithms on collections of up to 1 billion strings and compare their performance to other approaches on smaller datasets.We take further steps toward making the BWT a practical tool for processing string collections on this scale. First, we give two algorithms for recovering the strings in a collection from its BWT. Second, we show that if sequences are added to or removed from the collection, then the BWT of the original collection can be efficiently updated to obtain the BWT of the revised collection.

Cube root extraction in medieval mathematics

The algorithms used in Arabic and medieval European mathematics for extracting cube roots are studied with respect to algebraic structure and use of external memory (dust board, table, paper). They can be separated into two distinct groups. One contains methods used in the eastern regions from the 11th century, closely connected to Chinese techniques, and very uniform in structure. The other group, showing much wider variation, contains early Indian methods and techniques developed in central and western parts of the Arabic areas and in Europe. This study supports hypotheses previously formulated by Luckey and Chemla on an early scientific connection between China and Persia.

A scalable and embedded FPGA architecture for efficient computation of grey level co-occurrence matrices and Haralick textures features

This paper presents a novel and optimized embedded architecture based FPGA for an efficient and fast computation of grey level co-occurrence matrices (GLCM) and Haralick textures features for use in high throughput image analysis applications where time performance is critical. The originality of this architecture allows for a scalable and a totally embedded on Chip FPGA for the processing of large images. The architecture was implemented on Xilinx Virtex-FPGAs without the use of external memory and/or host machine. The implementations demonstrate that our proposed architecture can deliver a high reduction of the memory and FPGA logic requirements when compared with the state of the art counterparts and it also achieves much improved processing times when compared against optimized software implementation running on a conventional general purpose processor.

An efficient variable selection method based on the use of external memory in ant colony optimization. Application to QSAR/QSPR studies

A novel approach for the use of external memory in ant colony optimization strategy for solving descriptor selection problem in quantitative structure-activity/property relationship studies is described. In this approach, several ant colony system algorithms are run to build an external memory containing a number of elite ants. In the next step, all of the elite ants in the external memory are allowed to update the pheromones. Then the external memory is emptied and the updated pheromones are used again, by several ant colony system algorithms to build a new external memory. These steps are iteratively run for certain number of iterations. At the end, the memory will be containing several top solutions to the problem. The proposed approach was applied to solving variable selection problem in quantitative structure-activity/property relationship studies of rate constants of o-methylation of 36 phenol derivatives and activities of 31 antifilarial antimycin compounds, for which the obtained results revealed that both the speed and the solution quality are improved compared to conventional ant colony system algorithms.

A three-dimensional computational method for blood flow in the heart I. Immersed elastic fibers in a viscous incompressible fluid

This paper describes the numerical solution of the 3-dimensional equations of motion of a viscous incompressible fluid that contains an immersed system of elastic fibers. Implementation details such as vectorization and the efficient use of external memory are discussed. The method is applied to the damped vibrations of a fiber-wound toroidal tube, and empirical evidence of convergence is presented.