Use Of Application Specific Integrated Circuits Research Articles

FPGAs in Client Compute Hardware

FPGAs (field-programmable gate arrays) are remarkably versatile. They are used in a wide variety of applications and industries where use of ASICs (application-specific integrated circuits) is less economically feasible. Despite the area, cost, and power challenges designers face when integrating FPGAs into devices, they provide significant security and performance benefits. Many of these benefits can be realized in client compute hardware such as laptops, tablets, and smartphones.

ASIC-Resistance of Multi-Hash Proof-of-Work Mechanisms for Blockchain Consensus Protocols

Blockchain technology rapidly gained popularity based on its open and decentralized operation. Consensus protocol is the core mechanism of a blockchain network that securely maintains the distributed ledger from possible attacks from adversaries. Proof-of-work (PoW) is a commonly used consensus protocol that requires a significant amount of computation to find a new valid block. As the application-specific integrated circuits (ASICs) that are specially designed for PoW computation begin to dominate blockchain consensus operation, the decentralized nature of blockchain networks is being threatened. Many PoW mechanisms are being proposed to disincentivize the use of ASICs in the consensus operation. Employing multiple hash functions in the PoW computation (i.e., multi-hash PoW) is one of the commonly adopted approaches to achieve such ASIC-resistance. In this paper, we experimentally evaluate the level of ASIC-resistance of the multi-hash PoW mechanisms. We assess the level of ASIC-resistance based on the performance gap between ASICs and general-purpose computing platforms. Contrary to the expectation of the multi-hash PoW mechanisms, our results reveal that ASIC-resistance of these PoW mechanisms is not strong enough to prevent ASIC-based mining. Most of them show similar levels of ASIC-resistance as those of PoW mechanisms that are already defeated by ASIC-based systems.

A first-level calorimeter trigger for the ATLAS experiment

In the RD27 collaboration we have carried out system studies on the implementation of the first level calorimeter trigger processor system for the ATLAS experiment to be mounted at the Large Hadron Collider (LHC) at CERN. These studies suggest that the full system can be contained in six 18SU size crates which will process approximately 4000 electromagnetic and 4000 hadronic trigger cells and provide the central trigger processor (CTP) with signals from events with high-P/sub T/ electrons/photons, jets and missing-E/sub T/. A demonstrator trigger system operated successfully with the RD3 and RD33 calorimeters at the full 40 MHz LHC bunch crossing (BC) rate. The prototype application-specific integrated circuits (ASICs) in this system each processed data from only a single trigger cell and its environment, which would lead to an extremely large system for ATLAS. Using eight-bit parallel data even the use of ASICs, processing multiple trigger cells would demand unacceptably large numbers of input pins and module connections. Initial studies of this I/O problem produced a solution based on asynchronous transmission of zero-suppressed and BC-tagged data on 160 Mbit/s serial links. This approach appeared to be feasible but would have introduced additional latency of about 20 BCs. Further studies have led to the design of a fully-synchronous calorimeter trigger processor system using commercial high-speed optical links. The links will terminate in multi-chip modules (MCMs) incorporating custom-designed integrated optics, and the trigger algorithms will be implemented in ASICs. >

Reliability of asic devices

Abstract The use of application-specific integrated circuits (ASICs) has become widespread; from use in sophisticated telecommunications equipment through to children's toys. However, aspects of design, fabrication and testing may not be as rigorous as for the standard components that they are replacing. ASICs by their nature are usually low volume components and tend to be fabricated using the latest technology. However, the additional substantial costs involved with comprehensive reliability and quality assessment mean that testing is often less exhaustive, resulting in a product of uncertain reliability. Conventional wisdom states that fewer components will mean greater reliability; however if the devices are replaced by one of uncertain reliability, this will not necessarily be the case. This paper presents some considerations that should to be taken into account when contemplating the use of ASICs in place of conventional components. These are highlighted with specific examples seen at Telecom Austra...