Upcoming Technology Nodes Research Articles

Sensitivity analysis of methanol, chloroform, and dichloromethane using GAA-JLT-based gas sensor

Owing to the fact that the gate-all-around architecture is expected to prevail in the upcoming technology nodes, in this work we have taken up a simulation-based investigation on design of a gate-all-around junctionless transistor (GAA-JLT) based label-free gas sensor with conducting polymer (CP) gate. In the initial part of our work we have focused on the variation n device and sensor performance with initial work function of the CP, which depends upon its growth condition and primary doping. Interaction with various test gases modifies the CP characteristics, thereby changing its work function. Due to this a change in device characteristics is observed, which serves as the metric for assessing the GAA-JLT-based gas sensor performance. We have investigated the variation in device characteristics in the presence of different test gases. Further, the variation in sensor performance on interaction with the different test gases has been examined. The impact of operating conditions such as ambient temperature and partial pressure of the test gas on the sensing performance has been investigated. The impact of device dimension on the sensing performance has also been evaluated. Our computations reflect that tuning the initial work function of the CP by choosing the proper primary dopant concentration model along with proper tuning of the operating conditions can enhance the performance accuracy of the sensor.

Elucidating the Role of InGaAs and InAlAs Buffers on Carrier Dynamics of Tensile-Strained Ge Double Heterostructures.

Extensive research efforts of strained germanium (Ge) are currently underway due to its unique properties, namely, (i) possibility of band gap and strain engineering to achieve a direct band gap, thus exhibiting superior radiative properties, and (ii) higher electron and hole mobilities than Si for upcoming technology nodes. Realizing lasing structures is vital to leveraging the benefits of tensile-strained Ge (ε-Ge). Here, we use a combination of different analytical tools to elucidate the effect of the underlying InGaAs/InAlAs and InGaAs overlaying heterostructures on the material quality and strain state of ε-Ge grown by molecular beam epitaxy. Using X-ray analysis, we show the constancy of tensile strain in sub-50 nm ε-Ge in a quantum-well (QW) heterostructure. Further, effective carrier lifetime using photoconductive decay as a function of buffer type exhibited a high (low) defect-limited carrier lifetime of ∼68 ns (∼13 ns) in 0.61% (0.66%) ε-Ge grown on an InGaAs (InAlAs) buffer. These results correspond well with the measured surface roughness of 1.289 nm (6.303 nm), consistent with the surface effect of the ε-Ge/III-V heterointerface. Furthermore, a reasonably high effective lifetime of ∼78 ns is demonstrated in a QW of ∼30 nm 1.6% ε-Ge, a moderate reduction from ∼99 ns in uncapped ε-Ge, alluding to the surface effect of the overlying heterointerface. Thus, the above results highlight the prime quality of ε-Ge that can be achieved via III-V heteroepitaxy and paves a path for integrated Ge photonics.

Dissociative photoionization of phenyl triflate, a photoacid generator for photolithography, at 92 eV.

The dissociative photoionization of phenyl triflate (C6H5OSO2CF3), a neutral photoacid generator used in photolithography, was investigated in a gas phase experiment employing extreme ultraviolet (EUV) synchrotron radiation at 92eV and photoelectron-photoion coincidence detection. The interaction of EUV photons with the molecule leads almost exclusively to dissociation, which is dominated by a sequential fragmentation mechanism, in which SO2, CF3, CO, and C2H2 are lost. For lithographic purposes, the lack of the observation of a fragment that could serve as a precursor for the formation of triflic acid means that the effective photoacid generator concentration in a photoresist is reduced, impacting its patterning performance in EUV lithography. A better understanding of the dissociative photoionization of photoresist components and proxies thereof can provide a crucial handle that guides the design of photoresists for the upcoming technology nodes with ever decreasing feature sizes for more powerful computer chips.

Enhancement of Electromigration Reliability of Electroless-Plated Nanoscaled Copper Interconnects by Complete Encapsulation of a 1 nm-Thin Self-Assembled Monolayer

The downsizing of integrated circuits for the upcoming technology nodes has brought attention to sub-2 nm thin organic/inorganic materials as an alternative to metallic barrier/capping layers for nanoscaled Cu interconnects. While self-assembled monolayers (SAMs) serving as the barrier materials for copper metalized films are well studied, electromigration (EM) of Cu interconnects encapsulated by SAMs is an untouched research topic. In this study, we report an all-wet encapsulating process involving SAM seeding/encapsulating and electroless narrow-gap filling to fabricate nanoscaled copper interconnects that are completely encapsulated by a 1 nm-thin amino-based SAM, subsequently annealed to some extents prior to EM testing. Both annealing and SAM encapsulation retard EM of the Cu interconnects tested at current densities on orders of 108–109 A cm−2. Particularly, SAM encapsulation quintuples the lifetime of, for example, as-fabricated Cu interconnects from 470 to 2,890 s. Electromigration failure mechanisms are elucidated from analyses of activation energies and current-density scale factors obtained from the accelerated EM testing. The importance of SAM qualities (e.g., ordering and layered structure) as a prerequisite for the reliability enhancement cannot be overestimated, and the results of the SAM quality evaluation are presented. The mechanism of reliability enhancement is also thoroughly discussed.

(Invited) Strain-Related Peculiarities of B Incorporation in Epitaxial Si1-XGex Source/Drain Materials and Their Impact on Electrical Properties

New generations of CMOS field effect transistors (FET) impose stringent controls of device geometries and material properties. Moving towards more aggressively scaled dimensions increases the level of the different specifications to mitigate the contributions from parasitics and improve the performance. Device simulations for instance often emphasize performance degradations due to increasing contact resistances [1] and define contact resistivity targets for the upcoming technology nodes [2]. A significant step towards decreasing the metal-to-semiconductor contact resistivity and thereby alleviating these limitations can be achieved through high active doping concentrations within the p-type source / drain (S/D) layers e.g. in the case of pMOSFETs. This paper therefore focuses on strain-related effects influencing the incorporation of B dopants in SiGe S/D and on the consequences on the specific resistivity of Ti / SiGe:B contacts.We have shown in a previous contribution that strain relaxation leads to a decrease in B incorporation efficiency during the chemical vapor deposition of in-situ doped SiGe:B epilayers on Si(001) [3]. This negatively impacts the Ti / Si1-xGex:B contact resistivity. Similar behaviors were observed for three series of samples with compositions ranging from 25 to 65% Ge. The layers presented covered only a limited range of degrees of strain relaxation (DSR), e.g. up to ~ 30% in the case of Si0.5Ge0.5:B. In this paper, we extend these learnings by growing the different epitaxial materials on commercially available 300 mm strain-relaxed buffers (SRB). Three SRB compositions are used, with Ge contents of 25, 50 and 70%. They all present relatively low and well controlled threading dislocation densities (TDD) [4].Table 1 summarizes results obtained from Si0.5Ge0.5:B epilayers with nominal thicknesses of 20 and 50 nm. The resistivity of the layer grown on Si increases by ~ 10% when the DSR reaches 28% (partially relaxed material). This is due to a dynamic decay in B doping efficiency as the material relaxes, resulting in a reduced B surface chemical concentration ([B]chem,surf). The situation is however different when growing the S/D material on Si1-xGex SRB. This approach allows us to explore the impact of the substrate lattice parameter, thereby inducing a modification of the strain state at the growth start. As expected, reducing the compressive strain leads to lower B concentrations and increased resistivities. The new results therefore confirm the trends previously extracted in [3], where an increase in material resistivity was reported for layers with different Ge contents due to an increasing DSR. The extraction of similar [B]chem from Si0.5Ge0.5:B grown on Si and on Si0.75Ge0.25 SRB also indicates that misfit dislocations introduced by the SiGe / Si relaxation process do not play a significant role in the B incorporation efficiency. We infer that this assessment is important to understand in situ doping phenomena and address new device challenges. Acknowledgments: Gianluca Rengo received a PhD grant from the Flemish Research Foundation (FWO). All epitaxial depositions presented in this work were done in ASM Intrepid® reactors. The SiGe SRB wafers were provided by Siltronic. Clement Porret and Gianluca Rengo contributed equally to this work.

Investigation of Recessed Junctionless Double Gate MOSFET for Radio Frequency Applications

Junctionless Metal Oxide Semiconductor Field-Effect Transistor (JL MOSFET) is one of the promising candidate to replace the junction based MOSFET for upcoming technology nodes. Semiconductor industries are continuously urging for large ON current with the low OFF current and low specific on resistance. However, high ON current is achieved in Conventional (Conv.) JL DG MOSFET by using high doping concentration at the cost of high OFF current which leads depletion mode operation. Moreover, low doping, narrow channel thickness and high work function gate materials are using to operate Conv. JL DG MOSFET in enhancement mode (Vth > 0 V for N-JL DG MOSFET, Vth < 0 V for P-JL DG MOSFET) but ON current is reduced in all above mentioned solutions. To overcome the above mentioned problems, a new architecture is developed called Recessed JL DG MOSFET. In Recessed JL DG MOSFET silicon region is recessed under the gate region and some gate portion is extended towards source and drain region. Recessed JL DG MOSFET shows the same ON current as achieved in Conv. JL DG MOSFET with very low OFF current (leakage current) by considering high doping concentration. Surface potential, electron density, energy band distribution, drain current have been investigated to proof the enhancement mode operation of Recessed JL DG MOSFET. Figure of Merits (FOMs) for RF performance such as Trans-conductance, capacitance and intrinsic power gain (S21), Trans-conductance frequency product (TFP), Gain frequency product (GFP) and Gain trans-conductance frequency product (GTFP) have also investigated of Recessed JL DG MOSFET.

On the Workload Dependence of Self-Heating in FinFET Circuits

Self-heating effect (SHE) is a major reliability concern in current and upcoming technology nodes due to its ability to increase the channel's temperature of transistor and leading to degradations in the key electrical characteristics such as carrier mobility. In this brief, we study SHE in a full processor at the 7nm FinFET technology node. This is the first work to analyze the impact that executed workloads on top of processors have on stimulating SHE. As matter of fact, SHE in transistors is driven by the workload-induced switching activities. When it comes to evaluating SHE, state of the art typically assumes that the switching frequency f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sw</sub> and operating clock frequency f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">clk</sub> of a circuit are the same, concluding that SHE is not a concern in digital circuits that operate in the GHz-range like processors. After analysis a wide range of workloads, our investigation revealed that the majority of transistors in the processor's netlist exhibit a switching frequency in the kHz-range even though the processor's clock is in the GHz-range. This is because that the majority of transistors are within the data paths and hence their switching is driven by the workload data and not by the clock itself. In addition, we also demonstrate for the first time the important role that the duty cycle (on-/off-ratio) induced by the running workload has on modeling SHE. All in all, the relatively low switching activities together with skewed duty cycles induce a wide variety in channel temperatures. Thus, highlighting the importance of considering the workload when studying SHE.

Dynamic Guardband Selection: Thermal-Aware Optimization for Unreliable Multi-Core Systems

Circuit aging has become the major reliability concern in current and upcoming technology nodes. For instance, Bias Temperature Instability (BTI) leads to an increase in the threshold voltage of a transistor. That, in turn, may prolong the critical path delay of the processor and eventually may lead to timing errors. In order to avoid aging-induced timing errors, designers employ guardbands either with respect to voltage or frequency. State-of-the-art techniques determine a guardband type at the circuit level at design time irrespective from the running workload at the system level. Our investigation revealed that generated temperatures by a running workload have the potential to play a key role in determining the appropriate guardband type with respect to system performance. Therefore, we propose a paradigm shift in designing guardbands: to select the guardband types on-the-fly with respect to the workload-induced temperatures aiming at optimizing for performance under temperature and reliability constraints. Moreover, different guardband types for different cores can be selected simultaneously when multiple applications with diverse properties suggest this to be useful. Our dynamic guardband selection allows for a higher performance compared to techniques that employ a fixed (at design time) guardband type throughout.

Beam drift and partial probe coherence effects in EUV reflective-mode coherent diffractive imaging

While the industrial implementation of extreme ultraviolet lithography for upcoming technology nodes is becoming ever more realistic, a number of challenges have yet to be overcome. Among them is the need for actinic mask inspection. We report on reflective-mode lensless imaging of a patterned multi-layer mask sample at extreme ultraviolet wavelength that provides a finely structured defect map of the sample under test. Here, we present the imaging results obtained using ptychography in reflection mode at 6° angle of incidence from the surface normal and 13.5 nm wavelength. Moreover, an extended version of the difference map algorithm is employed that substantially enhances the reconstruction quality by taking into account both long and short-term variations of the incident illumination.

SiGe Heterojunction FinFET Towards Tera-Hertz Applications

In this work, a novel structure FinFET having an ultra-thin SiGe shell channel forming a heterojunction with Si core is proposed and characterized, with an emphasis on high-speed operation capability in the tera-hertz (THz) regime, by 3-dimensional (3-D) device simulation. The proposed device is operated in the p-type enhancement mode and the ultra-thin SiGe channel confines the mobile holes very effectively by the help of the valence band offset (VBO) between SiGe channel and Si core. The simulations with multiple drift and diffusion models and quantum mechanical models for higher accuracy allow to predict the minimum channel thickness and Ge content of 2 nm and 40%, respectively, for suppressing the hole leakage outflowing over the VBO. Also, scalability was checked down to 5 nm for achieving the upcoming logic technology nodes. Cut-off frequency (f T ) and maximum oscillation frequency (fmax) are obtained to be 240 GHz and 1.04 THz at a low drive voltage as −0.7 V, respectively.

The Impact of Dummy Gate Processing on Si-Cap-Free SiGe Passivation: A Physical Characterization Study on Strained SiGe 25% and 45%

High mobility channel materials like SiGe, Ge and IIIV receive lots of interest in order to enable the continuation of Moore’s path during the upcoming technology nodes. Recently Si-cap-free SiGe passivation with the number of interface states (NIT) down to 2 1011 cm-2 have been demonstrated. [1-3] A clear correlation was established between Ge-content in the SiGe-oxide and NIT. Unfortunately no process information has been provided on how the Ge-oxide-free interlayers were obtained. In a separate study the impact of HF, HCl and SC1 cleaning solution on the SiGe surface and oxide composition was reported. [4] A comparison of SiGe Gate-All-Around (GAA) and FinFET devices using a Si-cap-free SiGe 25% passivation scheme in a replacement metal gate (RMG) integration indicate the device performance is improved by a TMAH (aq) treatment prior to SiGe interlayer formation and high-k deposition. [5] Here the formation of a SiGe wet chemical oxide will be presented. The impact of dummy gate processing on the interlayer composition is reported. Also the impact of a TMAH (aq) treatment prior to chemical oxide formation has been analyzed and will be reported. Blanket strained SiGe 25% and 45% were grown by epitaxy. The SiGe-substrate and -oxide composition were measured by angle-resolved XPS using the Si2p and Ge3d peaks. The Ge3d peak is fitted with three different compounds: elemental Ge, GeO2 and Ge-suboxide. The angle dependence lets us estimate the distribution of the different components with respect to the sample top surface. An concentration increase with increasing angle (relative to the surface normal) indicates the compound is located closer to the sample surface. And reversely a concentration increase with increasing angle indicates the compound is located deeper into the sample. A native oxide was grown on SiGe 25 and 45% by exposing the wafers to the cleanroom air for approx. 1 week. The native oxide was found to be stoichiometric or nearly stoichiometric with a uniform Ge content throughout the oxide for SiGe 25 and 45% respectively. A wet chemical oxide was grown using an ‘imec clean’ [6] having a final O3/HCl (aq) rinse. The wet chemical oxide is Ge-poor compared to the SiGe substrate. No or only a small variation in Ge content of the SiGe-oxide is seen with ARXPS. However the fraction Ge-suboxide decreases with increasing angle, indicating the Ge-suboxide are located deeper within the sample, so closer to the SiGe-oxide/SiGe-substrate interface. The Ge-content of the SiGe-substrate after wet chemical oxidation shows a weak incident-angle-dependence, indicative a limited Ge enrichment of the SiGe substrate towards the SiGe-oxide/-substrate interface. The low Ge content of the SiGe-oxide is attributed to the water solubility of GeO2. The increase in Ge-content towards the SiGe-oxide/-substrate can be (at least partially) attributed to the poor water solubility of Ge-suboxide. The small increase in Ge content of the SiGe substrate can be attributed to the thermodynamically preferred oxidation of Si over Ge. The combined impact of dummy gate deposition, spike anneal and dummy gate removal prior to SiGe interlayer formation was investigated by AR-XPS and SIMS. The temperature used during spike anneal was found to have a significant impact on the Ge-content of the SiGe-oxide formed during an O3-last imec clean. The results will be reported in detail at the conference. The impact of TMAH (aq) on the chemical oxide composition and surface roughness will also be reported. TMAH (aq) was found to improve SiGe device performance. [5] Also the interaction with the subsequent HfO2 deposition will be reported. In summary SiGe is found to behave as a non-linear combination of Si and Ge. In HF-free aqueous solutions, the SiGe oxide composition is a combination of (1) thermodynamically preferred oxidation of Si versus Ge; (2) poor water-solubility of SiO2 and/or its low solubilization rate; and (3) fast dissolution of GeO2 but slow dissolution of Ge-suboxides. [1] CH Lee et al. VLSI 2016. [2] S. Siddiqui et al. presented MRS Spring Meeting 2016. [3] CH Lee et al. IEDM 2016. [4] S.L. Heslop et al. ECS Trans 69 (2015) 287. [5] H. Mertens et al VLSI 2015. [6] M. Meuris et al. Solid State Phenom, July 1995, p. 109. Figure 1

Scanning coherent diffractive imaging methods for actinic extreme ultraviolet mask metrology

For the successful implementation of extreme ultraviolet (EUV) lithography in the upcoming technology nodes, a major challenge to overcome is the stable and reliable detection and characterization of mask defects. We have recently presented a reflective mode EUV mask scanning lensless imaging tool (RESCAN) which was installed at the XIL-II beamline of the swiss light source and showed reconstructed aerial images of test patterns on EUV masks. RESCAN uses scanning coherent diffractive imaging (SCDI) methods to obtain actinic aerial images of EUV photomasks and was designed for 80 nm onmask resolution. Our SCDI algorithm reconstructs the measured sample by iteratively solving the phase problem using overdetermined diffraction data gathered by scanning across the specimen with a finite illumination. It provides the phase and amplitude aerial images of EUV photomasks with high resolution without the need to use high numerical aperture (NA) lenses. Contrary to scanning microscopy and full-field microscopy, where the resolution is limited by the spot size or NA of the lens, the achievable resolution with our method depends on the detector noise and NA of the detector. To increase the resolution of our tool, we upgraded RESCAN with a detector and algorithms. Here, we present the results obtained with the tool that is capable of up to 40-nm onmask resolution. We believe that the realization of our prototype marks a significant step toward overcoming the limitations imposed by methods relying on imaging optics and shows a viable solution for actinic mask metrology.

A 3-D CPU-FPGA-DRAM Hybrid Architecture for Low-Power Computation

The power budget is expected to limit the portion of the chip that we can power ON at the upcoming technology nodes. This problem, known as the utilization wall or dark silicon, is becoming increasingly serious. With the introduction of 3-D integrated circuits (ICs), it is likely to become more severe. Thus, how to take advantage of the extra transistors, made available by Moore’s law and the onset of 3-D ICs, within the power budget poses a significant challenge to system designers. To address this challenge, we propose a 3-D hybrid architecture consisting of a CPU layer with multiple cores, a field-programmable gate array (FPGA) layer, and a DRAM layer. The architecture is designed for low power without sacrificing performance. The FPGA layer is capable of supporting a large number of accelerators. It is placed adjacent to the CPU layer, with a communication mechanism that allows it to access CPU data caches directly. This enables fast switches between these two layers. This architecture reduces the power and energy significantly, at better or similar performance. This then alleviates the dark silicon problem by letting us power ON more components to achieve higher performance. We evaluate the proposed architecture through a new framework we have developed. Relative to the out-of-order CPU, the accelerators on the FPGA layer can reduce function-level power by $6.9\times $ and energy-delay product (EDP) by $7.2\times $ , and application-level power by $1.9\times $ and EDP by $2.2\times $ , while delivering similar performance. For the entire system, this translates to a 47.5% power reduction relative to a baseline system that consists of a CPU layer and a DRAM layer. This also translates to a 72.9% power reduction relative to an alternative system that consists of a CPU layer, an L3 cache layer, and a DRAM layer.

Delay/Power Modeling and Optimization of FinFET Circuit Modules under PVT Variations

The semiconductor industry has moved to FinFETs because of their superior ability to mitigate short-channel effects relative to CMOS. Thus, good FinFET delay and power models are urgently needed to facilitate FinFET IC design at the upcoming technology nodes. Another urgent problem that needs to be addressed with continued technology scaling is how to analyze circuit performance and power consumption under process, voltage, and temperature (PVT) variations. Such variations arise due to limitations of lithography that lead to variations in the physical dimensions of the device or due to environmental variations. In this article, we propose a delay/power modeling framework for analysis of FinFET logic circuits under PVT variations. We present models for FinFET logic gates and three FinFET SRAM cells. We use GenFin, which is a genetic algorithm based statistical circuit-level delay/power optimizer, to produce the models for functional units (FUs) employed in a processor. We compare the impact of PVT variations at the 22nm and 14nm FinFET technology nodes. We evaluate cache performance for various cache capacities and temperatures as well as that of FUs. Our device simulation results show that the 3σ/μ spread for 14nm circuits is, on average, 38.5% higher in dynamic power and 21.4% higher in logarithm of leakage power relative to 22nm FinFET circuits. However, the delay spread depends on the circuit.

Robust Design of High-Speed Interconnects Based on an MWCNT

A robust design of the propagation characteristics of interconnect structures based on multiwall carbon nanotubes (MWCNTs) is carried out. The study allows us to identify the minimum number of shells N of the MWCNT able to guarantee that the time delay at 50% outperforms the Cu-based solution for the upcoming technology nodes, taking into account the uncertainties affecting other geometrical and physical parameters of the device. Such an investigation is carried out in the most severe conditions for the MWCNTs-based device, i.e., for short and thin wire structures, starting from the minimum interconnect length for which the MWCNT outperforms the Cu-based solution. A worst case polynomial expression of the time delay as a function of the number of the shells of the MWCNT, obtained on the basis of the equivalent single conductor model of the nano-interconnect, is adopted for the optimization procedure. The minimum number of shells that lead to outperform the Cu-based solution is determined by the use of an approach relying on a particular application of the interval analysis to find the upper bound of the performance function. The quality of the results is checked by a Monte Carlo analysis.

Understanding the potential and limitations of HfAlO as interpoly dielectric in floating-gate Flash memory

Introduction of high-k dielectrics in Flash memory is seen as a must for the upcoming technology nodes. Hafnium aluminate (HfAlO) has been identified as a possible candidate for implementing the interpoly dielectric in floating gate memory. In this work, we establish a link between the material morphology and its electrical response, allowing to understand memory device behavior and to consequently assess the potential and limitations of HfAlO as IPD in a memory cell.