Untrusted Intellectual Property Research Articles

A Novel Low Complexity Logic Encryption Technique for Design-for-Trust

The outsourcing of several untrusted intellectual property designs makes the development of integrated circuits vulnerable to piracy, overbuilding, reverse engineering, and hardware Trojan (HT). To thwart the hardware-based attacks, several design-for-trust (DFT) techniques are reported in the literature. In this paper, we analyze that the existing methods are inefficient to prevent hardware Trojan attacks and also exhibit significant design overhead. Hence, we propose a novel DFT technique that effectively increases the immunity of design against the Trojan attack while requiring minimal overhead. In the proposed technique, various new light-weight key-gate topologies are proposed that effectively increase the triggering probability of Trojan at the rare-triggered nets by encrypting the design. We also propose a new encryption algorithm that identifies an optimal node using a new metric called vulnerability factor in-order to replace it with the proposed key-gate. Our encryption algorithm significantly reduces the number of vulnerable-nets with minimum replacements. The simulation results show that the proposed key-gates reduce on an average 34.2 percent and 35.1 percent per-gate area and energy respectively over the stack-based key-gates. Finally, our DFT technique gives on an average 94 percent area overhead reduction as compared to the best known DFT technique on the ISCAS-85 benchmarks.

Security Assurance for System-on-Chip Designs With Untrusted IPs

Modern system-on-chip (SoC) designs involve integration of a large number of intellectual property (IP) blocks, many of which are acquired from untrusted third-party vendors. An IP containing a security vulnerability-whether inadvertent or malicious-may compromise the trustworthiness of the entire SoC, e.g., by leaking sensitive information or causing execution failures at key points. Existing functional validation approaches, post-manufacturing tests, and IP trust verification techniques are inadequate to accomplish comprehensive system-level security assurance in the presence of untrusted IPs. In this paper, we analyze security issues at the SoC level caused by untrusted IPs. We also propose a novel, resilient SoC security architecture to ensure trusted SoC operation with untrusted IPs. Our architecture realizes fine-grained IP-trust aware security policies in an efficient security policy checker that enables run-time monitoring of security issues arising from untrusted IPs. It also exploits on-chip design-for-debug architecture to ensure trusted information flow from IP blocks to the security policy checker. Unlike existing solutions to the untrusted IP problem, which rely on verification of IP trust before they are integrated into an SoC, the proposed approach follows a fundamentally different architecture-level solution based on run-time resilience. We demonstrate the effectiveness of this framework for system protection using several illustrative practical use cases. We also provide experimental results to show that the overhead of the proposed architecture is modest on representative SoC designs.

基于混沌的公开可验证FPGA知识产权核水印检测方案

IP (intellectual property) infringement has been a serious problem to FPGA vendors or IP designer. Watermarking is a novel technique for FPGA IP protection, while existing FPGA watermarking techniques may give away sensitive information during the public verification (e.g. the content or position of watermarks), which enables malicious verifiers or third parties to remove the watermarks and resell the design. Existing zero-knowledge watermarking verification schemes are able to address the sensitive information leakage issue but are vulnerable to embedding attacks, which makes it ineffective in preventing denying infringement of un-trusted buyers (verifiers). This paper presents a new chaotic-based publicly verifiable zero knowledge watermark detection scheme for FPGA IP protection. This scheme is both resilient against the sensitive information leakage issue and removing attacks, thus robust to cheating from provers, verifiers or the third party. In traditional FPGA watermarking techniques, watermarks are embedded in the used Slices, thus the area overhead is proportional to the number of embedded watermarks. In the proposed scheme, watermarks are hidden in the unused LUTs of used Slices, introducing zero area and timing overheads. Chaotic systems are sensitive to initial values and convenient to produce numerous pseudo-random numbers with ultra-low coefficients and perfect statistical property. These advantages match the specific requirements for the random location permutation of the LUTs in the FPGA bit-stream file in the zero knowledge protocol, bringing an ultra-high robustness of LUT location permutation. The timestamp mechanism is also introduced in this paper to resist embedding attacks against denying the infringement from un-trusted IP buyers (verifiers). Experimental results and analysis show that the proposed scheme is significantly better than the latest related literatures in both watermarking overheads and robustness of location permutation.