Unnecessary Bits Research Articles

Near-lossless compression scheme using hamming codes for non-textual important regions in document images

Working at Bell Labs in 1950, irritated with error-prone punched card readers, R W Hamming began working on error-correcting codes, which became the most used error-detecting and correcting approach in the field of channel coding in the future. Using this parity-based coding, two-bit error detection and one-bit error correction was achievable. Channel coding was expanded further to correct burst errors in data. Depending upon the use of the number of data bits ‘d’ and parity bits ‘k’ the code is specified as (n, k) code, here ‘n’ is the total length of the code (d+k). It means that 'k' parity bits are required to protect 'd' data bits, which also means that parity bits are redundant if the code word contains no errors. Due to the framed relationship between data bits and parity bits of the valid codewords, the parity bits can be easily computed, and hence the information represented by 'n' bits can be represented by 'd' bits. By removing these unnecessary bits, it is possible to produce the optimal (i.e., shortest length) representation of the image data. This work proposes a digital image compression technique based on Hamming codes. Lossless and near-lossless compression depending upon need can be achieved using several code specifications as mentioned here. The achieved compression ratio, computational cost, and time complexity of the suggested approach with various specifications are evaluated and compared, along with the quality of decompressed images.

A Study on the Concept of Using Efficient Lightweight Hash Chain to Improve Authentication in VMF Military Standard

Authentication algorithms in the form of cryptographic schemes, such as the Secure Hash Algorithm 1 (SHA-1) and the digital signature algorithm (DSA), specified in the current variable message format (VMF) military standard have numerous reliability-related limitations when applied to tactical data link (TDL) and multi-TDL networks (MTN). This is because TDL and MTN require maximum tactical security, communication integrity, and low network overhead based on many protocol header bits for rapid communication with limited network resources. The application of such authentication algorithms to TDL and MTN in a rapidly changing battlefield environment without reinforcement measures will lead to functional weaknesses and vulnerabilities when high-level digital-covert activities and deception tactics are implemented. Consequently, the existing VMF authentication scheme must be improved to secure transmission integrity, lower network transaction, and receive authentication tactical information in VMF-based combat network radio (CNR) networks. Therefore, in this study, a tactical wireless ad hoc network topology, similar to that of the existing CNRs, is considered, and a lightweight multi-factor hash chain-based authentication scheme that includes a time-based one-time password (T-OTP) for network overhead reduction and terminal authentication is proposed, coupled with exception handling. The proposed method enhances the confidentiality of tactical message exchanges and reduces unnecessary network transactions and transmission bits for authentication flows between real-time military terminals owned by squads, while ensuring robustness in limited battlefields. Based on these approaches, in the future, we intend to increase the authentication reliability between wireless terminals in the Korean variable message format (KVMF)-based CNR networks based on the Korean Army Corps network scenarios.

Generalization of SPIHT: Set Partition Coding System.

This paper constructs a set partition coding system (SPACS) to combine the advantages of different types of set partition coding algorithms. General tree (GT) is an important conception introduced in this paper, which can represent tree set and square set simultaneously. With the help of GT, SPIHT is generalized to construct degree- k SPIHT based on the analysis of two kinds of set partition operations. Using the same coding mechanism, SPACS (k,p) is constructed, aided with virtual subbands that are generated by recursive division on the LL band. SPACS belongs to tree-set partition coding algorithms if k and p take smaller values. In particular, SPACS(2,1) is the classical SPIHT. SPACS tends toward a block-set partition coding algorithm as k,p increases. Location bit, amplitude bit, and unnecessary bit are presented, which can be used to analyze the coding efficiency of SPACS. We compress 256 images with 512×512 using SPACS. The numerical results show SPACS achieves some improvements in coding efficiency over SPIHT, especially at very low bitrate. On average, to code every image, SPACS(3,1) (at an average of 3.93 bpp) needs 7792 more location bits but saves 10 218 unnecessary bits, compared with SPIHT (3.94 bpp).

ICAT: Engine to Perform Range Analysis and Allocate Bit-Widths for Arithmetic Datapaths

Range analysis determines allocation of fixed-point integer bit-widths, which is critical for arithmetic on fixed-point representations. The traditional methods, either simulation-based or static, can be time-consuming and produce coarse bounds, potentially leading to large error bounds and unnecessary bits. In this paper, we propose a new static method to perform fixed-point range analysis towards obtaining the tighter ranges efficiently. The hybrid method, ICAT, combines four techniques, including Interval arithmetic, consistency checking, affine arithmetic and arithmetic transform and is the only method that is aware how far it is from the exact solution. For the benchmarks available with comparable methods, we show that the bit-width allocation can be obtained with better results, and in shorter execution time.

Efficient depth coding in 3D video to minimize coding bitrate and complexity

In three-dimensional video (3DV) coding, color videos and depth maps both need to be coded. Usually, two-channel coding method is used in the system of 3DV coding which encodes color videos and depth maps based on two parallel codec implements. The complexity and hardware requirements are nearly two times higher than coding the 2D color video. Meanwhile, depth maps in 3DV usually are estimated from color video data and the estimated depth itself can be very noisy. In this paper, we propose fast and effective depth coding to minimize depth coding bitrate and the coding complexity. The 3?×?3 bilateral filter is first utilized to pre-process depth maps to reduce noises from the depth estimation procedure, and thus unnecessary bits to code depth noises can be reduced. Meanwhile, there is a high correlation among motion information from color videos and depth maps. Coding information including motion vectors and the prediction mode is drawn from the color video to accelerate the mode decision procedure of depth coding and reduce the temporal variation of depth maps. Experimental results show that the proposed algorithm can reduce 70% computational complexity of depth coding and 20% depth bitrate.

REDUCING THE ENERGY DISSIPATION OF THE ISSUE QUEUE BY EXPLOITING NARROW IMMEDIATE OPERANDS

In contemporary superscalar microprocessors, issue queue is a considerable energy dissipating component due its complex scheduling logic. In addition to the energy dissipated for scheduling activities, read and write lines of the issue queue entries are also high energy consuming pieces of the issue queue. When these lines are used for reading and writing unnecessary information bits, such as the immediate operand part of an instruction that does not use the immediate field or the insignificant higher order bits of an immediate operand that are in fact not needed, significant amount of energy is wasted. In this paper, we propose two techniques to reduce the energy dissipation of the issue queue by exploiting the immediate operand files of the stored instructions: firstly by storing immediate operands in separate immediate operand files rather than storing them inside the issue queue entries and secondly by issue queue partitioning based on widths of immediate operands of instructions. We present our performance results and energy savings using a cycle accurate simulator and testing the design with SPEC2K benchmarks and 90 nm CMOS (UMC) technology.

Sidney's “Insertour”: Arcadia, Parenthesis, and the Formation of English Eloquence

This essay reads Philip Sidney's Arcadia as a translation of the figure parenthesis, a rhetorical scheme that inserts allegedly unnecessary bits of text into an already complete sentence. This logic of insertion not only conditions the narrative structure of the Arcadia but also shapes Sidney's revisions to the romance, which insert vast amounts of new material before abruptly breaking off in mid‐parenthesis. The supplementary logic of parenthesis continues to operate after Sidney's death, organizing the various prose continuations inserted into the printed Arcadia in the seventeenth century. By explicating the rhetorical work done by a figure that is usually dismissed as a source of syntactical confusion, this essay attempts to make sense of Sidney's ubiquitous “half Moons.” (J.C.M.)

Low-power multiplierless DCT architecture using image correlation

Low-power design is one of the most important challenges to maximize battery life in portable devices and to save the energy during system operation. In this paper, we propose a low-power DCT (discrete cosine transform) architecture using a modified multiplierless CORDIC (coordinate rotation digital computer) arithmetic. The switching power consumption is reduced during DCT: the proposed architecture does not perform arithmetic operations of unnecessary bits during the CORDlC calculations. The experiment results show that we can reduce up to 26.1% power dissipation without compromise of the final DCT results. Also, the speed of the proposed architecture is increased about 10%. The proposed low-power DCT architecture can be applied to consumer electronics and portable multimedia systems requiring high throughput and low-power.