Universal Asynchronous Receiver Transmitter Research Articles

A Review on Design and Verification of Programmable UART with AXI

A Review on Design and Verification of Programmable UART with AXI

FPGA-base object tracking: integrating deep learning and sensor fusion with Kalman filter

This research presents an integrated approach for object detection and tracking in autonomous perception systems, combining deep learning techniques for object detection with sensor fusion and field programmable gate array (FPGA-based) hardware implementation of the Kalman filter. This approach is suitable for applications like autonomous vehicles, robotics, and augmented reality. The study explores the seamless integration of pre-trained deep learning models, sensor data from a depth camera, real-sense D435, and FPGA-based Kalman filtering to achieve robust and accurate 3D position and 2D size estimation of tracked objects while maintaining low latency. The object detection and feature extraction are implemented on a central processing unit (CPU), and the Kalman filter sensor fusion with universal asynchronous receiver transmitter (UART) communication is implemented on a Basys 3 FPGA board that performs 8 times faster compared to the software approach. The experimental result provides the hardware resource utilization of about 29% of look-up tables, 6% of lookup table RAMs (LUTRAM), 15% of Flip-flops, 32% of Block-RAM, 38% of DSP blocks operating at 100 MHz, and 230400 baud rates for the UART. The whole FPGA design executes at 2.1 milliseconds, the Kalman filter executes at 240 microseconds, and the UART at 1.86 milliseconds.

Universal Asyncronous Receiver Transmitter

Abstract: This project focuses on the Verilog-based design and implementation of a Universal Asynchronous ReceiverTransmitter (UART) communication module. The UART is a fundamental component in digital systems, facilitating serial data transmission between devices. Our objective is to develop a robust and efficient Verilog description of the UART module, emphasizing simplicity, modularity, and ease of integration. The baud rate generator allows for flexible communication speeds, accommodating diverse applications. The module ensures accurate framing of transmitted and received data through the proper generation of start and stop bits. Error-detection mechanisms are implemented to enhance data integrity. The project enhances the digital design field by delivering a Verilog implementation of a UART communication module that is both dependable and efficient.

Design, refinement, and enhancement of FPGA-implemented UART circuitry

This article provides an overview of the universal asynchronous receiver/transmitter, commonly referred to as Universal Asynchronous Receiver/Transmitter (UART). The UART stands as a noteworthy exemplar of a serial communication protocol, facilitating the exchange of data within a serial connection while accommodating full-duplex communication. The architecture of the UART hinges upon three principal constituents: the transmitter, the receiver, and the baud rate generator, the latter essentially a frequency divider. Each of these elements is meticulously crafted using the Verilog hardware description language, thereby ensuring distinct and efficient design. Furthermore, this discourse delves into refined iterations of these implementations. For instance, it introduces the concept of a baud rate self-adaptive function and expounds upon multibyte transmission techniques. In a concerted effort to streamline circuit design and curtail the electro circuit's footprint, a deliberate decision is made to forgo the integration of a parity check module. Consequently, the chosen data format is the widely adopted 8N1 (8 data bits, 1 stop bit and no parity bit) configuration.

An FPGA-Based Adaptive Solution for Synchronous Configuration in UART Communication

To address the challenges associated with data reception failures, which arise due to abrupt alterations in the baud rate and the data format of the transmission signal in traditional Universal Asynchronous Receiver-Transmitter (UART) scenarios, this study presents an adaptive UART parameter solution underpinned by Field-Programmable Gate Array (FPGA) technology. Initially, this manuscript elucidates the underlying principles of UART communication and delineates the pivotal constituents of the UART protocol. Subsequently, it offers an in-depth analysis, from the transmission perspective, of how specific parameters influence the effectiveness of the UART protocol. Based on the software and hardware embodiments associated with the dual primary functions – baud rate adaptation and data format adaptation – this paper extensively details the flow chart for baud rate adaptation, the circuitry for edge detection, methodologies for baud rate computation, and the parameter eigenvalue approach. Following this, Verilog, a hardware description language, is employed for coding and subsequent simulation within the Quartus II environment. Empirical evidence corroborates the efficacy of the proposed design in achieving synchronous configuration between the baud rate and the data format. The findings of this research bear substantial implications for augmenting both the adaptability and dependability of UART communication systems.

A Comparative Analysis of Synchronous USART And Asynchronous UART Communication Protocols

In contemporary applications, the integration of the STM32F103ZET6 microcontroller with various peripherals is indispensable, emphasizing the critical role of serial communication in data transmission between the microcontroller and these peripherals. This study delineates the distinctions between Universal Synchronous Asynchronous Receiver-Transmitter (USART) and Universal Asynchronous Receiver-Transmitter (UART) within the context of USART synchronous communication. The superiority of USART is underscored by its utilization of a uniform clock and identical baud rate for simultaneous and synchronous transmission, enhancing data transfer efficiency significantly. This methodology facilitates the transmission of larger data quantities concurrently and mitigates data loss during prolonged transmission, a prevalent issue in UART asynchronous communication. Additionally, USART preserves essential functionalities such as the detection of data boundaries, automatically discerning the initiation and termination of individual data frames, which guarantees the uninterrupted reception and transmission of data. This analysis is pivotal for professionals seeking optimized communication protocols in microcontroller-based systems.
 In contemporary applications, the integration of the STM32F103ZET6 microcontroller with various peripherals is indispensable, emphasizing the critical role of serial communication in data transmission between the microcontroller and these peripherals. This study delineates the distinctions between Universal Synchronous Asynchronous Receiver-Transmitter (USART) and Universal Asynchronous Receiver-Transmitter (UART) within the context of USART synchronous communication. The superiority of USART is underscored by its utilization of a uniform clock and identical baud rate for simultaneous and synchronous transmission, enhancing data transfer efficiency significantly. This methodology facilitates the transmission of larger data quantities concurrently and mitigates data loss during prolonged transmission, a prevalent issue in UART asynchronous communication. Additionally, USART preserves essential functionalities such as the detection of data boundaries, automatically discerning the initiation and termination of individual data frames, which guarantees the uninterrupted reception and transmission of data. This analysis is pivotal for professionals seeking optimized communication protocols in microcontroller-based systems.

Comparison And Selection of Commonly Used Communication Protocols in Measurement and Control Instruments

In the contemporary landscape of economic globalization, the salience of the field of measurement and control has progressively intensified. Simultaneously, the utilization of serial bus technology within instrumentation has witnessed a considerable proliferation. Consequently, the judicious selection of an appropriate serial bus protocol has assumed paramount importance. It is incumbent upon practitioners to consider diverse factors, including the communication principles, performance attributes, and interfacing requirements, when making their choice, to ensure the efficacious and stable operation of their systems. This investigation employs a methodology that amalgamates a comprehensive literature review with experimental comparative analyses to ascertain the optimal suitability of Universal Asynchronous Receiver/Transmitter (UART), Inter-Integrated Circuit (I2C), and Serial Peripheral Interface (SPI) communication protocols across distinct application scenarios. Subsequent to a thorough comparative scrutiny, this study ultimately elucidates the respective merits and demerits of the UART, I2C, and SPI communication protocols, in tandem with their most judicious application contexts. This research endeavor serves to furnish engineers with valuable insights for the judicious selection of serial bus protocols.

Bidirectional Multi-Device Daisy Chain Communication Architecture and Verification Based on UART Serial Communication Protocol

This paper proposes an innovative bidirectional multi-device daisy chain communication framework grounded in the Universal Asynchronous Receiver-Transmitter (UART) serial communication protocol. This intricate architecture employs four distinct physical Input/Output (IO) interfaces to facilitate dynamic serial communication amongst multiple devices. These devices can be conjoined in a sequential daisy chain or in a closed-loop ring configuration. To further enhance the functionality, our system incorporates a unique mechanism that leverages randomized device codes for rapid address allocation. This not only facilitates directional communication but also supports broad-spectrum broadcast transmissions. An exhaustive simulation of the said protocol was carried out utilizing Proteus software in tandem with a Microcontroller Unit (MCU) model. Critical parameters such as communication response delay, the cumulative failure rate of transmissions, and the isolated failure rate of individual data packets between nodes were meticulously evaluated. Preliminary findings underscore the protocol's potential in fostering cost-effective and dependable communication amongst a plethora of devices. The practicality and versatility of this system manifest prominently in arenas like cluster robot command, robotic automation, and holistic environmental monitoring.

A multi-microcontroller-based hardware for deploying Tiny machine learning model

<span lang="EN-US">The tiny machine learning (TinyML) has been considered to applied on the edge devices where the resource-constrained micro-controller units (MCUs) were used. Finding a good platform to deploy the TinyML effectively is very crucial. The paper aims to propose a multiple micro-controller hardware platform for productively running the TinyML model. The proposed hardware consists of two dual-core MCUs. The first MCU is utilized for acquiring and processing input data, while the second is responsible for executing the trained TinyML network. Two MCUs communicate to each other using the universal asynchronous receiver-transmitter (UART) protocol. The multi-tasking programming technique is mainly applied on the first MCU to optimize the pre-processing new data. A three-phase motors faults classification TinyML model was deployed on the proposed system to evaluate the effectiveness. The experimental results prove that our proposed hardware platform was improved 34.8% the total inference time including pre-processing data of the proposed TinyML model in comparing with single micro-controller hardware platform.</span>

A Systematic Analysis of The UART Transceiver Theory and Application

This article introduces the theoretical foundation and application of Universal Asynchronous Receiver/Transmitter (UART) in four chapters, including the history and structure of UART transceivers, and so on. UART is a kind of communication hardware using serial Asynchronous communication, which has the advantages of simple structure and good stability. It can convert serial data and parallel data to each other and transmit data between devices. It is widely used on various devices. In the 50 years since its invention, it has undergone many improvements and improvements. In the end, UART transceivers became one of the extremely important hardware in modern electronic technology. At present, UART transceivers are applied in many fields, including healthcare, the Internet of Things, and avionics. Its application in the fields of healthcare and the Internet of Things is of great significance, providing more possibilities for a more convenient life for humanity. Meanwhile, researchers are also attempting to continue improving the transmission speed of UART transceivers and reducing their power consumption.

Analysis of the baud rate of the UART to affects the data

This article explores the impact of different baud rates on Universal Asynchronous Receiver/Transmitter (UART) asynchronous serial communication. It discusses the frame format and calculation method of baud rate error, as well as the main reasons for error, such as clock error, sampling error, line noise, data bit error, and software delay. To ensure reliable communication, it is essential to test and debug the actual baud rate and adjust it accordingly. The study found that higher expected baud rates resulted in higher baud rate errors, affecting transmission distance, speed, reliability, and system complexity. The appropriate baud rate should be selected based on specific application scenarios and requirements. Higher baud rates are needed for high-speed transmissions, while lower baud rates are required for long transmission distances or high reliability requirements. However, further research is needed to determine the impact of unallocated baud rates on data. Overall, this article provides valuable insights into the development of UART.

Managing Concurrent Queues for Efficient In- Vehicle Gateways

In modern vehicles, electrical control units communicate over multiple in-vehicle networks via domainor zone-oriented gateway architectures. This work examines efficient frame transfer across incoming and outgoing Controller Area Network (CAN) interfaces at a gateway. In our embedded platform prototype, each CAN interface of a CAN-to-CAN gateway is controlled independently by a corresponding Portable Operating System Interface (POSIX) thread. Inter-thread communication and synchronization are implemented using shared data structures, either lock-free concurrent queues or traditional lock-based circular queues that embody single-producer single-consumer (SPSC) principles. Our experimental framework provides a realistic open automotive platform that integrates multiple CAN interfaces. An Odroid XU3 device acts as a gateway, providing two Universal Asynchronous Receiver- Transmitter (UART) to CAN interfaces that lead to Raspberry Pi 3B nodes (connected to CAN via Serial Peripheral Interface (SPI)). To increase communication reliability and performance by minimizing frame loss and improving the egress CAN frame rate, low-level parameters at the gateway are optimized, especially the inter-character delay of the UART-to-CAN interfaces. Our experiments show that the frame waiting time in the queue is shorter for the concurrent queue, while relaying messages is equally fast, reaching a maximum output rate of ~380 frames/s for large enqueue rates near saturation. Power consumption is almost four times higher for the concurrent queue implementation.

Design And Implementation of UART Based on Verilog HDL

As a two-way transmission channel, Universal Asynchronous Receiver/Transmitter (UART) not only greatly improves the efficiency of information transmission between computers and external devices, but also ensures the accuracy and consistency of information by eliminating metastable state, setting baud rate and other means. In this paper, on the basis of fully understanding the definition and function of UART, based on Verilog HDL language to build UART, and through Modelsim simulation, image and data. The experimental results show that the receiving and sending module of this module works well and meets the requirements of full-duplex serial communication equipment. There is no doubt that the design of this paper has made a more detailed explanation of the basic operating principle of UART, which will contribute to its further development.

Real-time performance improvement approach based on FPGA in OFDR system

This paper presents a novel approach to accelerate the data processing rate in optical frequency-domain reflectometry (OFDR) system. In conventional solution, data is sampled by data acquisition card and then sent to personal computer (PC) for data processing through high-speed interface such as peripheral component interconnect express (PCIE) and so on. But frequently-used general laptop can’t provide this interface. What’s more, long time is necessary to complete the calculation in PC due to the limitations of serial processing in central processing unit (CPU). To improve the real-time performance of OFDR system, in our work, field-programmable gate array (FPGA) is used as hardware circuit to complete the calculation task and then send the results to PC only to display through universal asynchronous receiver/transmitter (UART) interface in the OFDR system simultaneously. In this way, the refresh rate of output can be accelerated about 50 times, which means the real-time performance of the system is improved a lot.

Implementation of the advanced encryption standard algorithm on an FPGA for image processing through the universal asynchronous receiver-transmitter protocol

<span lang="EN-US">Communication among end users can be based either on wired or wireless technology. Cryptography plays a vital role in ensuring data exchange is secure among end users. Data can be encrypted and decrypted using symmetric or asymmetric key cryptographic techniques to provide confidentiality. In wireless technology, images are exchanged through low-cost wireless peripheral devices, such as radio frequency identification device (RFID), nRF, and ZigBee, that can interface with field programmable gate array (FPGA) among the end users. One of the issues is that data exchange through wireless devices does not offer confidentiality, and subsequently, data can be lost. In this paper, we propose a design and implementation of AES-128 cipher algorithm on an FPGA board for image processing through the <a name="_Hlk107307233"></a>universal asynchronous receiver transmitter (UART) protocol. In this process, the advanced encryption standard (AES) algorithm is used to encrypt and decrypt the image, while the transmitter and receiver designs are implemented on two Xilinx BASYS-3 circuits connected with a ZigBee RF module. The encrypted image uses less memory, such as LUTs (141), and also consumes less chip power (0.0291 w), I/O (0.003), block RAM (0.001 w), data, and logic to provide much higher efficiency than wired communication technology. We also observe that images can be exchanged through the UART protocol with different baud rates in run time.</span>

A Custom Parallel Hardware Architecture of Nonlinear Model-Predictive Control on FPGA

This article presents the field-programmable gate array (FPGA) implementation of a particle swarm optimization (PSO)-based nonlinear model-predictive control (NMPC) for applications with millisecond timescales and resource-constrained embedded systems. A custom hardware circuit architecture of an NMPC controller, which mainly includes phase-locked loop clock, universal asynchronous receiver transmitter interface, trigonometric function, random number generator, objective function, and PSO solver modules, is implemented on the FPGA based on a hardware description language specification. It employs parallelism, pipelining, and specialized numerical formats to enhance the online computation performance of NMPC. In addition, the partial parallel expansion calculations of the fitness (objective) function and the particle position update are adopted for trading off the computational performance against resource usage. The hardware-in-the-loop experimental results through controlling a wheeled mobile robot model demonstrate that the design is capable of computing the required control action in real time by using a midrange FPGA, while still offering good control performance.

Energy-Efficient UART Design on FPGA Using Dynamic Voltage Scaling for Green Communication in Industrial Sector

In the present scheme of the world, the problem of shortage of power is seen across the world which can be a vulnerability to various communication securities. The scope of proposed research is that it is a step towards completing green communication technology concepts. In order to improve energy efficiency in communication networks, we designed UART using different nanometers of FPGA, which consumes the least amount of energy. This shortage is happening because of expanding of industries across the world and the rapid growth of the population. Therefore, to save the power for our upcoming generation, the globe is moving towards the concept and ideas of green communication and power-/energy-efficient gadget. In this work, a power-efficient universal asynchronous receiver transmitter (UART) is implemented on 28 nm Artix-7 field-programmable gate array (FPGA). The objective of this work is to reduce the power utilization of UART with the FPGA device in industries. To do this, the same authors have used voltage scaling techniques and compared the results with the existing FPGA works.

Automated Identification of Application-Dependent Safe Faults in Automotive Systems-on-a-Chips

ISO 26262 requires classifying random hardware faults based on their effects (safe, detected, or undetected) within integrated circuits used in automobiles. In general, this classification is addressed using expert judgment and a combination of tools. However, the growth of integrated circuit complexity creates a huge fault space; hence, this form of fault classification is error prone and time consuming. Therefore, an automated and systematic approach is needed to target hardware fault classification in automotive systems on chips (SoCs), considering the application software. This work focuses on identifying safe faults: the proposed approach utilizes coverage analysis to identify candidate safe faults considering all the constraints coming from the application. Then, the behavior of the application software is modeled so that we can resort to a formal analysis tool. The proposed technique is evaluated on the AutoSoC benchmark running a cruise control application. Resorting to our approach, we could classify 20%, 11%, and 13% of all faults in the central processing unit (CPU), universal asynchronous receiver–transmitter (UART), and controller area network (CAN) as safe faults, respectively. We also show that this classification can increase the diagnostic coverage of software test libraries targeting the CPU and CAN modules by 4% to 6%, increasing the achieved testable fault coverage.

RISC-V Hardware Synthesizable Processor Design Test and Verification Using User-Friendly Desktop Application

Although the RISC-V ISA has not been around for long, it is a processor architecture that has been highlighted by many businesses and individuals for its low-cost and rapid pace of development. They are open-source-synthesizable hardware processors with minimal functionality that is ideal for current IoT applications involving simple sensors and actuator controls. Due to some qualities of hardware, they can operate in areas where software programs and applications cannot be used whereas, these software programs that run on such hardware equally help in understanding how hardware operates. This paper, therefore, proposes and discusses the design, implementation, and internal verification and test platform for a Reduced Instruction Set Code-V’s (RISC-V) Instruction Set Architecture (ISA), using an interactive desktop program for a 32-bit single-cycle processor. This paper developed a system that functions as interactive assistance to RISC-V's ISA design and debugger using a more user-friendly desktop UI application. The uniqueness of this design is the flexibility of testing and debugging that is possible through either the software interface or through hardware peripherals such as Universal Asynchronous Receiver/Transmitter (UART) protocols in FPGA or even both. These peripherals allow users to view the contents of the register files and RAM being utilized by the implemented processor on the FPGA. The proposed desktop User Interface program monitors and controls the sequential processing and states of a 32-bit single-cycle RISC-V processor’s operation on an FPGA. Contents of the proposed processor’s registers and memory are displayed alongside other temporal or internal data. Internal components such as Program Counters (PC), Random Access Memory (RAM), are displayed all through the proposed User Interface (UI) program and also through various peripherals on the FPGA board. The software program is implemented using C# programing language through Microsoft Visual Studio 2019 Integrated Development Environment (IDE). The proposed hardware synthesizable processor core is implemented using Verilog Hardware Description Language (HDL) and synthesized with Xilinx Integrated Synthesis Environment (ISE) version 14.7. The proposed processor and its corresponding hardware test modules occupy 6476 Look-Up-Tables (LUT) and operate at a maximum frequency of 49MHz and its operation is verified on a Field Programmable Gate Array (FPGA). The proposed processor and its test platform can serve as a good educational tool as well as a help for processor design engineers both experienced and beginners.

Design and Implementation of Power-Efficient FSM based UART

The remarkable innovations in technology are driven mainly by the high-speed data communication requirements of the modern generation. The Universal Asynchronous Receiver Transmitter (UART) is one of the most sought-after communication protocols. This work mainly focuses on implementing and analysing the UART for data communication. The Finite State Machine (FSM) implements the baud rate generator, transmitter, and receiver modules. Cadence NCSIM was utilized for simulation, and Cadence RTL Compiler was used during synthesis using the 45 nm and 90 nm General Process Design Kit (GPDK) library files. The baud rate of 9600 bps and 50 MHz clock frequency was used to design UART. The increased speed and complexity of the VLSI chip designs has resulted in a significant increase in power consumption. The comparative analysis of power and delay for different clock periods shows an improvement in the total power and the Power Delay Product (PDP) with increasing clock periods. Better results were observed using 45 nm in comparison to the 90 nm library.