Universal Asynchronous Receiver And Transmitter Research Articles

High Speed UART Implementation Using VHDL

Abstract: The Universal Asynchronous Receiver and Transmitter (UART) could be a custom designed circuit that allows serial communication between a laptop and a computer peripheral. The complex nature of combined circuit generation has made machine design time consuming at the gate and switch flop levels. As a results of this reality, the style designer made the choice to use hardware description language during the virtual machine layout process. VHDL could be a hardware description language that's accustomed model digital systems. It contains information that you just may find useful. It includes information which will be accustomed explain the virtual machine's behaviour shape, also because the ability to explicitly specify its timing. VHDL could be a difficult and verbose language with many complicated assembles that have complicated semantic meanings and is difficult to grasp initially. The language facilitates hierarchical machine modelling likewise as top don methodologies. It provides an easier method for checking the UART and assisting within the discovery of any discrepancies. It also allows for a more behavioural explanation of the module's characteristics. It makes the look implementation easier to read and understand, and it also provides the flexibility to simply describe dependencies among numerous procedures that arise in complex eventdriven systems. Thus, the layout employs VHDL as a layout language to reap the transmitter module. First, the running version of the transmitter is defined. Then, using VHDL, all of the transmitter's blocks are designed and defined.

Area Optimization using Structural Modeling for Gate Level Implementation of SPI for Microcontroller

The need for miniaturization has been the driving force in chip manufacturing. The proliferation of IoT, robotics, consumer electronics and medical instruments pose unprecedented demands on the embedded system design. The area optimization can be achieved either by reducing the size of transistors or by optimizing (reducing) the circuit at the gate level. The first solution has attracted many researchers while the later has not been explored to its full potential. The aim is to design a System on Chip (SoC) to satisfy the dynamic requirements of disruptive technologies while occupying the lesser area. The design and testing of communication interfaces such as Serial Peripheral Interface (SPI), Inter-IC Communication (I2C), Universal Asynchronous Receiver and Transmitter (UART) are very crucial in the area optimization of microcontroller design. Since SPI being an important communication protocol, this work reports the preliminary research carried in the design and verification of it. In this work, Verilog is used for the design and verification of the SPI module. The results show that there is a drastic reduction in the number of Look-Up-Tables (LUTs) and slices required to build the circuit. We conclude that sophisticated optimization techniques of the circuit at the gate level has the potential to reduce the area by half.

SoEasy: A Software Framework for Easy Hardware Control Programming for Diverse IoT Platforms.

Many Internet of Things (IoT) applications are emerging and evolving rapidly thanks to widespread open-source hardware platforms. Most of the high-end open-source IoT platforms include built-in peripherals, such as the universal asynchronous receiver and transmitter (UART), pulse width modulation (PWM), general purpose input output (GPIO) ports and timers, and have enough computation power to run embedded operating systems such as Linux. However, each IoT platform has its own way of configuring peripherals, and it is difficult for programmers or users to configure the same peripheral on a different platform. Although diverse open-source IoT platforms are widespread, the difficulty in programming those platforms hinders the growth of IoT applications. Therefore, we propose an easy and convenient way to program and configure the operation of each peripheral using a user-friendly Web-based software framework. Through the implementation of the software framework and the real mobile robot application development along with it, we show the feasibility of the proposed software framework, named SoEasy.

STM32 프로세서를 이용한 고속 데이터 수집 및 융합 시스템 설계

In this paper, we describe the design of a high speed data acquisition system(DAS) with STM32 processor based on Cortex-M4. The system is used for the sensor devices to collect raw data on production lines at factory and send them to the servo computer in real time. The system is designed for multi functions with universal asynchronous receiver and transmitter(UART), analog to digital converter(ADC), digital to analog converter(DAC), and general purpose input output(GPIO). those are well tested for various data acquisition and high speed motor control in real time.

Communications Link Design and Analysis of the NEXTSat-1 for SoH File and Mission Data Using CAN Bus, UART and SerDesLVDS

The communications link in a space program is a crucial point for upgrading its performance by handling data between spacecraft bus and payloads, because spacecraft`s missions are related to the data handling mechanism using communications ports such as a controlled area network bus (CAN Bus) and a universal asynchronous receiver and transmitter (UART). The NEXTSat-1 has a lot of communications ports for performing science and technology missions. However, the top level system requirements for the NEXTSat-1 are mass and volume limitations. Normally, the communications for units shall be conducted by using point to point link which require more mass and volume to interconnect. Thus, our approach for the novel communications link in the NEXTSat-1 program is to use CAN and serializer and deserializer low voltage differential signal (SerDesLVDS) to meet the system requirements of mass and volume. The CAN Bus and SerDesLVDS were confirmed by using already defined communications link for our missions in the NEXTSat-1 program and the analysis results were reported in this study in view of data flow and size analysis.

Design of a micro-UART for SoC application

This paper presents the design of a universal asynchronous receiver and transmitter (UART), which is fully functional and synthesizeable. Due to its modularity, configurability and extremely compact size, the proposed UART is named as micro-UART and it is ideal for system-on-a-chip (SoC) application. The core is usable as an intellectual property. Verilog hardware description language (HDL) in the Altera's MAX-PLUS II environment has been used for its design, compilation and simulation. The UART has been implemented using Altera's FPGA technology.

Design of a micro-UART for SoC application

This paper presents the design of a universal asynchronous receiver and transmitter (UART), which is fully functional and synthesizeable. Due to its modularity, configurability and extremely compact size, the proposed UART is named as micro-UART and it is ideal for system-on-a-chip (SoC) application. The core is usable as an intellectual property. Verilog hardware description language (HDL) in the Altera's MAX-PLUS II environment has been used for its design, compilation and simulation. The UART has been implemented using Altera's FPGA technology.