Unity Voltage Gain Research Articles

Asymmetric Half-Frequency Modulation in DAB to Optimize the Conduction and Switching Losses in EV Charging Applications

Dual active bridge (DAB) DC-DC converters are used widely in electric vehicle (EV) charging systems with the advantage of high-power density, bidirectional power flow, and possibility of soft-switching. The Maximum converter efficiency of DAB-based EV chargers happens at unity voltage gain, while it degrades at the start of the charging cycle where the gain is lower. This paper presents a novel gate signal modulation method called asymmetric half-frequency modulation (AHFM) that modifies the duty ratio and switching frequency of the source bridge switches to achieve the higher converter efficiency at low gain operation. Generalized harmonic approximation (GHA) method is utilized to analyze the circuit operation with applied AHFM, and evaluation of zero voltage switching (ZVS) requirements is explained. Then, a loss optimization problem is developed with an objective to select the optimal set of phase shift control variables depending on the modulation method to minimize the sum of conduction and switching losses. Five modulation methods based on conventional modulation and proposed AHFM are compared in terms of resultant switching network efficiency at a wide gain/power range that gives an understanding of optimal method at a specific operating point. The proposed AHFM and loss optimization are applied to the EV battery charging profile to improve the converter efficiency during the whole charging cycle. A 1.1 kW-rated proof-of-concept DAB DC-DC converter has been developed to validate the performance of the proposed method.

(Invited) New Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs, Considering a Wide Range of High Temperatures

The 1st generation of innovative gate layout styles for MOSFETs have proven to be able to enhance the electrical performance and tolerance to ionizing radiation of analog MOSFETs. This paper presents the 2nd one. It preserves the new effects of the 1st generation and is able to further reduce the Leff of MOSFETs in relation to those achieved by the 1st generation, considering a wide range of high temperatures. We observe that the Half-Diamond layout style is able to boost the saturation drain current and the unity voltage gain frequency by up to 52.4% and 75%, respectively. Therefore, this technique remains an alternative to improve the electrical performance of analog MOSFETs, mainly for space, nuclear and medical CMOS ICs applications. Figure 1

High-uniformity 2 × 64 silicon avalanche photodiode arrays with silicon multiple epitaxy technology

In this paper, high-uniformity 2×64 silicon avalanche photodiode (APD) arrays are reported. Silicon multiple epitaxy technology was used, and the high performance APD arrays based on double-layer epiwafers are achieved for the first time, to the best of our knowledge. A high-uniformity breakdown voltage with a fluctuation of smaller than 3.5 V is obtained for the fabricated APD arrays. The dark currents are below 90 pA for all 128 pixels at unity gain voltage. The pixels in the APD arrays show a gain factor of larger than 300 and a peak responsivity of 0.53 A/W@M = 1 at 850 nm (corresponding to maximum external quantum efficiency of 81%) at room temperature. Quick optical pulse response time was measured, and a corresponding cutoff frequency up to 100 MHz was obtained.

Feasibility Analysis of a Reduced Capacitive Wireless Power Transfer System Model for Transportation Electrification Applications

A practical approach in modeling a capacitive wireless power transfer (CPT) system that utilizes an electrostatic field for the power transfer is presented in this article. The reduced capacitance model (RCM) is derived from the conventional six capacitance model (SCM) for the CPT system in view of the large charging area applications, such as electric vehicle charging. The effect of the same side and cross-coupling capacitances diminishes when the separation distance between the same side plate pair is large enough, and the reduced capacitance model (RCM) is obtained. A bipolar capacitive-link dispersion distance proposed in this article acts as an indicator to decide the use of RCM or SCM depending on the application. Furthermore, RCM attains unity voltage gain and load-independent operation at the designed single resonant frequency, unlike the SCM, where the influence of multiple resonant frequencies is predominant. An experimental validation is performed to determine the effectiveness of the RCM.

Lateral separate absorption charge multiplication Ge-on-Si avalanche photodiode with low dark current in linear mode

To suppress the dark current and improve the detection sensitivity of the Germanium-on-silicon (Ge-on-Si) avalanche photodiode (APD), we report an integrated waveguide-based Ge-on-Si APD with a lateral separate absorption charge multiplication (SACM) structure, which works at low bias voltage. The breakdown voltage (Vbr) of the lateral SACM APD in linear mode is about 5.81 V, and the device demonstrates very low dark current of 0.157 nA and 40.7 nA at unity gain voltage (VGain=1=3.5 V) and 0.95Vbr (∼5.5 V), at room temperature. We also study the single photon detection performance of the device in Geiger mode. The practical dark count rate (DCR) at 300 K is with the same order of magnitude as the vertical SACM Ge-on-Si APD operating at 200 K. With the wavelength and average photon number of weak coherent pulse are 1550 nm and 0.1, respectively, the theoretical single photon detection efficiency (SPDE) of the device can achieve 0.4% at 300 K, which will reduce the dependence of the weak light detection system on the low-temperature working environment.

Germanium-on-silicon avalanche photodiode for 1550 nm weak light signal detection at room temperature

To optimize the dark current characteristic and detection efficiency of the 1550 nm weak light signal at room temperature, this work proposes a Ge-on-Si avalanche photodiode (APD) in Geiger mode, which could operate at 300 K. This lateral separate absorption charge multiplication APD shows a low breakdown voltage (Vbr) in Geiger mode of -7.42 V and low dark current of 0.096 nA at unity gain voltage (VGain=1 = -7.03 V). Combined with an RF amplifier module and counter, the detection system demonstrates a low dark count rate (DCR) of 1.1×106 counts per second and high detection efficiency η of 7.8% for 1550 nm weak coherent pulse detection at 300 K. The APD reported in this work weakens the dependence of the weak optical signal recognition on the low environment temperature and makes single-chip integration of the single-photon level detection system possible.

A Single Parameter Voltage Adjustable Immittance Topology for Integer- and Fractional-Order Design Using Modular Active CMOS Devices

A simple single parameter adjustable immittance concept designed with modular active devices, fabricated in I3T $25~0.35~\mu \text{m}$ 3.3 V CMOS process of ON Semiconductor, is introduced. The proposed devices employ an integer-order capacitor and specifically designed fractional-order capacitors (sometimes called constant phase elements). The proposed active topology consists of two simple active elements, namely a linearly voltage adjustable operational transconductance amplifier and a voltage differencing unity gain voltage follower/buffer, and only two passive elements, i.e. redundancy is minimized. The designed topology offers generation of an adjustable immittance having both the capacitive and inductive character. The importance of the order as well as the value of the pseudo-capacitance for design and analyzes are shown, including all important parasitic features for estimation of expected operational bandwidth which have to be considered in the design. The operational bandwidth is determined by high values of approximants of fractional-order capacities (225, 56 and $8.8~\mu \text{F}$ /sec^1- $\alpha $ , where $\alpha $ represents the order equal to 0.25, 0.5 and 0.75, respectively). These parameters result into ranges between tens of Hz and units-tens of kHz. The adjustability of the transconductance from 70 to $700~\mu \text{S}$ by the driving voltage between 0.05 and 0.5 V offers approximately one decade change of equivalent capacitance and inductance. Laboratory-based experiments done with a fabricated prototype confirmed the theoretical presumptions.

Light-Load Efficiency Enhancement of High-Frequency Dual-Active-Bridge Converter Under SPS Control

Dual-active-bridge (DAB) converter is an attractive topology to be used as a dc transformer (DCT) in the dc power distribution system. Because the voltage gain for dc transformer is relatively fixed, single-phase-shift (SPS) control is popularly adopted for the DAB converter to achieve simple power control. Aiming at increasing the light load efficiency of high-frequency DAB converter under SPS control, this letter proposes a concept to achieve full load range zero-voltage-switching (ZVS) with minimum rms current in certain voltage variation range. In the proposed method, the added magnetizing inductance creates the possibility to achieve ZVS for all power switches. The voltage gain of the converter is specially controlled by turns ratio, which is no longer the conventional unity voltage gain condition. The key parameters optimization, including the turns ratio, magnetizing inductance, and leakage inductance of the transformer, is introduced based on ZVS and current stress analysis. A 250 kHz, 400/48 V, 1000 W GaN-based DAB prototype is built, which shows performance improvements at light load.

Controller design, analysis and testing of a three‐phase VSI using IDA–PBC approach

A voltage-source inverter (VSI) is a key component of a distributed generation unit and an uninterruptible power supply. In this study, a three-phase VSI control using interconnection and damping assignment passivity-based control (IDA-PBC) approach has been revisited and analysed on aspects such as voltage gain, output impedance, transient response, stability and steady-state error. It is shown that in the case of accurately known filter parameters and perfectly zero initial conditions, theoretically, the voltage controller would exhibit unity voltage gain and zero output impedance. It is also shown that the IDA-PBC-based voltage controller exhibits a second-order response to a step input. This property has been utilised to propose a novel systematic procedure for tuning of the IDA-PBC gains based on the transient response specifications. The tuning method reveals that the gains for the outer voltage and inner current loops are related to each other and should not be separately tuned. The presented analysis and the proposed tuning method for controller gain have been tested through simulation studies. The concepts were further validated on a laboratory scale prototype of a three-phase VSI for balanced, unbalanced and non-linear loads.

Novel Active-Neutral-Point-Clamped Inverters With Improved Voltage-Boosting Capability

Conventional active-neutral-point-clamped (ANPC) inverters exhibit low voltage gain that inherently leads to a high dc-link voltage requirement. An improved ANPC inverter that is capable of generating five voltage levels has recently reduced the dc-link voltage twofold to achieve unity gain. This led to the development of a single-stage dc–ac power converter with no frontend boost dc–dc converter. This article proposes novel ANPC inverters capable of unity or boosted voltage gain while generating higher voltage levels. The first topology can provide a voltage gain of 1.5 and extends the number of levels to seven by incorporating only one additional switch. The topology can also be extended by adding three switches and one floating capacitor to generate nine levels with unity voltage gain, or 11 levels with a voltage gain of 2.5. The proposed ANPC inverters and their operations are comprehensively discussed. Experimental results are provided to validate the feasibility of the proposed ANPC inverters.

Wireless Electric Vehicle Battery Charging System using PV Array

Objectives: Wireless Power Transfer (WPT) technology is developing rapidly in Electrical Vehicle applications. Along with WPT, the benefits of Photovoltaic (PV) array are exploited and a system is proposed for extracting the power from PV array to charge the Electric Vehicle (EV) battery through Series-Series compensated network in WPT mode. Methods/Analysis: Recently, resonance phenomenon is widely used in transferring power efficiently to the load over a large air gap. Since, various reactive components contribute to resonance, there are many resonating frequencies. Hence, a frequency analysis of series-series compensator is carried out. The proposed system is simulated in Powersim (PSIM) software and the experimental set up has been built and tested in the laboratory. Findings: Frequency analysis of the proposed system helps in identifying the operating frequency at which the resonance with unity voltage gain is achieved irrespective of load variations in Series-Series wireless power transmission systems. Both simulation and experimental results are furnished in this paper for validating the proposed system. Applications/Improvements: As the power transfer is in wireless mode, the proposed system can be used in any climatic conditions for charging the EV. Also, closed loop controllers can be developed for improving the performance of the proposed system.

Novel Loss and Harmonic Minimized Vector Modulation for a Current-Fed Quasi-Z-Source Inverter in HEV Motor Drive Application

The recently proposed current-fed quasi- Z-source inverter (QZSI) can buck and boost voltage and provide bidirectional power flow . A crucial criterion for the size of three-phase PWM converters is the cooling of the power semiconductors and thus determination of power dissipation at certain operating points. In the modified space vector PWM method (SVPWM) control method for this circuit, different PWM sequences can lead to different switching loss, current ripple, total harmonic distortion, and also the voltage spike on the switching devices. In order to select the best PWM sequence to obtain the best performance and efficiency, a complete analysis and calculation for the four mentioned criterions are presented for different sequences. For each criterion, the best sequences are selected to obtain better performance. Finally, the optimized PWM sequence in the modified SVPWM control for this circuit is selected with the optimized hardware design together to achieve the best efficiency at the full operation range. The optimized hardware design has been built in the lab, including the optimal design of the coupled inductor, optimal design and selection of Z-source capacitors and output capacitors, the selection of Z-source diode, and the final layout of the hardware. In order to bring the prototype into real application in a hybrid electrical vehicle , the inverter efficiency is measured according to the motor P-V curve. The estimated efficiency curve and experiment results are plot and compared. The best efficiency at 15 kW reaches 97.6% at unity voltage gain.

Experimental Study of the OCTO SOI nMOSFET and Its Application in Analog Integrated Circuits

This paper presents an experimental comparative study between the OCTO, Diamond and Conventional Silicon-On-Insulator nMOSFETs (OSM, DSM and CSM, respectively), considering the same bias condition for all devices. The first comparison between the OSM and the CSM counterpart considers the same gate area and the second between the OSM and DSM regards the same geometric factor, in order to verify the benefits of the octagonal gate geometry, that uses the longitudinal corner effect to increase the resultant longitudinal electric field along of the channel, to improve the device performance and consequently to enhance the performance of analog integrated circuits. These characteristics can be observed on the main analog parameters such as drain current in saturation region, maximum transconductance, transconductance by drain current, voltage gain, unity voltage gain frequency and Early voltage.

Usando um voltímetro para medir tempo

As vezes, para se medir um intervalo de tempo, é suficiente um cronômetro, outras vezes é preciso imaginar ou lançar mão de métodos indiretos. Neste trabalho exploramos um método indireto para medir intervalos de tempo baseado na curva de descarga de um capacitor através de um resistor. O capacitor, previamente carregado, esta ligado em série com o resistor e uma chave apropriada inicialmente aberta. Quando a chave é acionada durante um certo tempo, o capacitor perde parte de sua carga e a tensão nos seus terminais cai para um valor V. Medindo-se a tensão inicial V0 e a tensão V, determina-se a partir da curva de descarga ou da equação de descarga de um capacitor num circuito RC o tempo t durante o qual a chave permaneceu fechada. O método consiste justamente em associar a duração de um evento ao tempo t durante o qual a chave permaneceu fechada. Para medir V e V0 sem que o capacitor se descarregue através da resistência interna do voltímetro, acoplamos a ele um amplificador operacional (CA 3140), montado na configuração seguidor emissor. O método foi testado com sucesso numa série de experiências que realizamos. Numa delas, por exemplo, medimos a duração de uma colisão entre duas esferas de aço e, numa outra, medimos a velocidade de um projétil disparado por uma carabina de pressão.

A class of digitally programmable nth‐order filters

SUMMARYA family of new high‐order filters capable of providing all filter functions without changing the circuit topology is proposed for integrated circuit applications. The proposed filters are based on simple active elements, namely, digitally controlled current amplifiers (DCCAs) and unity gain voltage buffers (VBs). Gains of DCCAs are digitally programmed to adjust the coefficients of transfer functions. R2R ladders are also utilized to increase the tuning flexibility of the proposed filters. A filter replicating the famous KHN biquad is extended to realize general nth‐order filters. Comparison with the recent works shows that the proposed approach results in more efficient realizations compared with its counterparts based on other current‐mode active elements. Experimental results obtained from a fourth‐order filter implemented using devices fabricated in a 0.35‐µm CMOS process are provided. Copyright © 2011 John Wiley & Sons, Ltd.

Measuring Frequency Response of a Single-Walled Carbon Nanotube Common-Source Amplifier

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Frequency response function (FRF) showing ac gain from a single-walled carbon nanotube transistor is presented. A top-gated carbon nanotube FET (CNFET) is configured as a common-source amplifier and the FRF of the amplifier is measured. Evidence of unambiguous signal amplification is observed in time domain as well as frequency domain up to a unity voltage gain frequency of approximately 560 kHz. The observed roll-off in frequency is solely due to the <emphasis emphasistype="italic">RC</emphasis> time constant of the measurement apparatus. A specifically designed circuit-compatible SPICE model for the CNFET is used to model both dc and ac characteristic with the same set of physical parameters. Good agreement between measurement and simulation is obtained. For a device without the parasitic load capacitance, we predict an intrinsic unity voltage gain frequency of 29 GHz and a cutoff frequency of <formula formulatype="inline"><tex Notation="TeX">$\sim {50}$</tex></formula> GHz. </para>

Power-efficient class AB CMOS buffer

A novel class AB unity gain voltage buffer is proposed. It is based on the use of quasi-floating gate (QFG) techniques in a super source follower topology. The circuit achieves dynamic current boosting with accurate control of quiescent currents and without penalty in supply voltage requirements or quiescent power consumption. Measurement results of the circuit, fabricated in a 0.5 µm CMOS technology, show a slew-rate enhancement by a factor 18.5 against the conventional super source follower, for the same bias current and supply voltage.

New Single-Resistance-Controlled Oscillator Configurations Using Unity-Gain Cells

Unity-gain voltage followers and unity-gain current followers have attracted attention in the recent literature in the context of analog signal processing as well as signal generation because of the advantages of wider bandwidth and low power consumption of these active elements as compared to other more complex building blocks. Motivated by these advantages, followers have been used as alternatives to other more complex building blocks in the realisation of filters, oscillators and more recently, in impedance converters. Although some configurations for realizing sinusoidal oscillators using unity-gain voltage/current followers have been described in the earlier literature, only one of them is a second-order single-resistance-controlled oscillator but requires as many as eight followers. This paper derives, through a state-variable synthesis approach, a number of new follower-based single-resistance-controlled oscillators requiring a much smaller number (only two to four) of followers. The new circuits are shown to possess a number of other interesting features. The workability of the new structures has been confirmed by SPICE simulation results using CMOS-based followers.

Novel sinusoidal oscillators using only unity-gain voltage followers and current followers

Two novel configurations of second-order sinusoidal oscillators have been presented which employ only unity-gain voltage followers and current followers as active elements. The workability of the new circuits has been demonstrated by the SPICE simulations of their CMOS-implementable versions.

New single resistance controlled oscillators employing a reduced number of unity-gain cells

Recently, the authors introduced two new second-order single-resistance-controlled oscillators (SRCO) employing four/three unity-gain cells (unity-gain voltage followers and unity-gain current followers). In this communication, a novel family of SRCOs has been presented which employ a reduced number of (only two) unity-gain cells as active elements. The workability of the new circuits has been confirmed by the SPICE simulations of their CMOS-implementable versions.