Unity Gain Frequency Research Articles

Comparison of Si CMOS and SiC CMOS Operational Amplifiers

In this study, we numerically compare the characteristics of Si and SiC CMOS operational amplifiers (OpAmp) using LTspice. According to prior researches, we set the device parameters for Si and SiC MOSFETs. The OpAmp consists of three stages: the input stage, the gain stage, and the output stage. We established three criteria for the OpAmp's operation: (1) a unity gain frequency of 1MHz, (2) an open-loop gain of at least 75dB, and (3) a phase margin of more than 60° when a load capacitance is 300pF. To achieve a unity gain frequency of 1MHz, we adjusted the values of the resistor and capacitor used for phase compensation. The supply voltage was set to be ±5V for the Si OpAmp and ±15V for the SiC one. Our numerical analysis of the frequency response shows that the Si OpAmp met all three criteria. In contrast, the SiC OpAmp, when faced with a load capacitor of 300pF, had a phase margin of 43.4°, falling below the 60° mark. For the SiC OpAmp, the frequency response declined rapidly when the supply voltage dropped to 10V or below.

Ultra-low-power super class-AB adaptive biasing operational transconductance amplifier with enhanced gain for biomedical applications

The operational transconductance amplifier (OTA) proposed in this article is a bulk-driven (BD), single-stage, super-class-AB, adaptive biasing, functioning in the subthreshold region (ST) with an enormously low power supply of ± 0.25 V, providing high-gain. The input core of the OTA circuit is composed of adaptively biased BD differential input pairs based on flipped voltage follower (FVF), which drive in class-AB mode with a partial positive feedback (PPF) approach. The circuit additionally employs FVF and self-cascode (SC)-based low-power current mirror loads at its output to obtain significantly high gain and unity gain frequency. In addition, using adaptive loads based on source-degenerated metal oxide semiconductor (MOS) resistors raises dynamic current more efficiently, consequently improving the slew rate and unity gain frequency (UGF) without drawing additional power. Employing the cadence spectre tool and the UMC 0.18 μm complementary metal oxide semiconductor (CMOS) process technology, the designed OTA has been simulated. The simulation outcomes substantiate that the amplifier provides high open loop DC gain of 75 dB, 18.75 kHz UGF with a phase margin of 63.93º, and input-referred noise (IRN) of 0.734 µV/Hz0.5 at 1 kHz frequency. The proposed OTA consumes just 60.15 nW of power. The performance results confirmed that the proposed OTA circuit is appropriate in biomedical applications.

GaAs-on-insulator based vertical heterojunction tunnel FET: proposal and analysis for VLSI circuit applications

This work analyses the Gallium Arsenide (GaAs)-on-insulator based vertical heterojunction tunnel FET with Gallium Antimonide (GaSb) as source material and GaAs as channel/drain material (GaSb/GaAs VTFET) to enhance the performance of the device and is compared with the Silicon-based VTFET. Silvaco Atlas TCAD tool is employed to perform numerical calculations. Tentative fabrication process flow of GaSb/GaAs VTFET is presented. GaSb is a low bandgap material that enhances the tunneling of charge carriers at source-channel heterojunction. GaSb/GaAs VTFET device outperforms Si-based VTFET in terms of electrical performance metrics such as ON-state current (ION), and ION/IOFF increases by a factor of 11 and 270 respectively; whereas OFF-state current (IOFF), subthreshold swing (SS), threshold voltage (VT) and drain-induced barrier lowering (DIBL) reduce by 95.98%, 39.36%, 17.14% and 29.17% respectively. Further, analog/RF and linearity/distortion performance analysis is carried out. GaSb/GaAs VTFET has improved analog/RF performances in terms of cut-off frequency (fT), gain-bandwidth product (GBP), transit time (τ), device efficiency (DE), transconductance frequency product (TFP) and suppressed distortions in compare to Si-based VTFET. Finally, GaSb/GaAs VTFET is evaluated for process variations and designing digital inverter and common source amplifier circuits. The Look-up-table (LUT) based Verilog-A model within the CADENCE tool has been employed to scrutinize the transient responses of inverter and common source amplifier circuits. Unity gain frequency and 3-dB bandwidth obtained for GaSb/GaAs VTFET amplifier are 15 GHz and 5.97 GHz. Therefore, this work presents GaSb/GaAs VTFET’s strong candidature for analog and digital VLSI circuit designing.

A 0.3 V OTA with Enhanced CMRR and High Robustness to PVT Variations

In this paper, we present a 0.3 V body-driven operational transconductance amplifier (OTA) that exploits a biasing approach based on the use of a replica loop with gain. An auxiliary amplifier is exploited both in the current mirror load of the first stage of the OTA and in the replica loop in order to achieve super-diode behavior, resulting in low mirror gain error, which enhances CMRR, and robust biasing. Common-mode feedforward, provided by the replica loop, further enhances CMRR. Simulations in a 180 nm CMOS technology show 65 dB gain with 2 kHz unity-gain frequency on a 200 pF load when consuming 9 nW. Very high linearity with a 0.24% THD at 90% full-scale and robustness to PVT variations are also achieved.

Electrical performance estimation and comparative study of heterojunction strained and conventional gate all around nanosheet field effect transistors

Abstract In this paper, we propose a novel type of Gate All Around Nanosheet Field Effect Transistor (GAA NS FET) that incorporates source heterojunctions and strained channels and substrate. We compare its electrical characteristics with those of the Heterojunction Gate All Around Nanosheet Field Effect Transistor (Heterojunction GAA NS FET) and the Conventional Gate All Around Nanosheet Field Effect Transistor (Conventional GAA NS FET). We investigate the impact of electrostatic control on both DC and analog parameters such as gate capacitance (C gg), transconductance g m, and cut-off frequency (f T) for all three device types. In our Proposed GAA NS FET, we employ Germanium for the source and substrate regions, Silicon/Germanium/Silicon (Si/Ge/Si) for the channel, and Silicon for the drain region. The introduction of strain into the nanosheet and the use of a heterojunction structure significantly enhance device performance. Before utilizing a model to analyze a semiconductor device, it is crucial to accurately determine and elaborate on the model parameters. In this case, we solve the Density Gradient (DG) equation self-consistently to obtain the electrostatic potential for a given electron Fermi-level distribution, use the Shockley-Read-Hall (SRH) equation to estimate carrier generation, account for bandgap narrowing in transport behavior, and consider auger recombination. Our general results indicate a notable improvement in drain current, transconductance, and unity-gain frequency by approximately 42%, 53%, and 31%, respectively. This enhancement results in superior RF performance for the Proposed GAA NS FET compared to both the heterojunction GAA NS FET and the conventional GAA NS FET.

Four stage CMOS operational amplifier, frequency compensated via active miller network

AbstractA four‐stage CMOS operational amplifier is proposed in this work. The designed amplifier is frequency compensated via two differential blocks and two Miller capacitors. Unlike well‐known frequency compensation methods, the proposed compensation leaves the output node while exploiting extremely smaller capacitors compared to conventional approaches. The presented approach is modeled symbolically and realized at the circuit level via the Hspice circuit simulator and 0.18 μm CMOS technology. Good agreements between two separate simulation paths verify the validity and accuracy of the proposed approach. Ample simulation results are reported to investigate the proposed amplifier regarding parameter mismatches. According to the simulation results, the proposed four‐stage amplifier is an excellent candidate to be used in larger systems such as data converters, modulators, and sensors while it shows more than 169 dB as DC‐gain, 10 MHz as unity gain frequency with power consumption less than 500 μW.

Experimental study of MISHEMT from 450 K down to 200 K for analog applications

This work presents an experimental analysis of Metal-Insulator-Semiconductor High Electron Mobility transistor (MISHEMT) operating in a temperature range from 450 K down to 200 K, focusing on analog applications. The drain current and consequently the saturation transconductance (gmsat) showed to be slightly dependent on gate length. The output conductance (gD) presents a higher dependence with gate length than gmsat for the whole temperature range due to the influence of MOS conduction that is strongly affected by short channel effect. There is also a kink in the behavior of these parameters at 350 K, most likely due to the competition of temperature effects on different conduction mechanisms. The transistors showed a good performance in terms of analog application, where the intrinsic voltage gain (AV) increases from 38 dB (at 200 K) to 43 dB (at 450 K) for 800 nm gate length while the unity gain frequency (fT) decreases from 1.8 GHz (at 200 K) to 800 MHz (at 450 K) for a gate length of 400 nm, which makes MISHEMT a good candidate for analog applications.

DC and RF Performance of an N-channel Monolayer Black Phosphorus Nanoribbon Transistor

Two-dimensional black phosphorus is a relatively new discovery. There are numerous studies on black phosphorus two-dimensional transistors that focus on analog and RF performance. However, the RF performance of black phosphorus nanoribbon transistors is yet to be explored. We use a four-band tight binding Hamiltonian in conjunction with a non-equilibrium Green's function quantum transport simulator to investigate both the DC and RF performance of a monolayer black phosphorus nanoribbon transistor. We found that electron intra-band tunneling is responsible for current flow in the off-state, while in the on-state, the electrons flow over the top of the channel barrier potential. With a VDD of 0.4 volt and a gate length of 5 nm, our black phosphorus nanoribbon transistor has DC performance metrics of 510 µA/µm on-state current, 105 on/off current ratio, and 65 mV/dec inverse subthreshold slope. The device's RF performance characteristics are as follows: cut-off (unity current gain) frequency of 772.84 GHz, maximum oscillation (unity power gain) frequency of 1.15 THz, and open circuit voltage gain of 26.7 dB with transistor operating in the on-state. The RF performance of the device is found to be significantly impacted by the source and drain contact resistances. With source and drain resistances set to zero, the cut-off frequency increases to 995.23 GHz and the unity power gain frequency increases to 4.16 THz. The device shows unconditional stability above 893 GHz and it is conditionally stable below this frequency.

СХЕМОТЕХНИЧЕСКИЕ МЕТОДЫ ПОВЫШЕНИЯ БЫСТРОДЕЙСТВИЯ ОПЕРАЦИОННЫХ УСИЛИТЕЛЕЙ НА ОСНОВЕ «ПЕРЕГНУТОГО» КАСКОДА

Three circuit techniques are proposed that provide (with simultaneous use) an increase bymore than two orders of magnitude of the maximum output voltage slew rate (SR) of microelectronicoperational amplifiers (op-amps) based on bipolar transistors with a classical architecture,designed to operate in automatic control systems, radio engineering and communications, forexample, as drivers for ultra-high-speed analog-to-digital converters (EVIOAS150, EVIOAS350,AD9208, AD9691, 1273PV14, etc.). The considered op-amps contain a cascode input stage with anon-linear correction of the pass-through characteristic and a tracking circuit that increases theattenuation coefficient of the input common-mode signals and the noise suppression coefficient onthe power buses, as well as an intermediate stage based on a “folded” cascode. The use of a"folded" cascode makes it possible to increase the efficiency of using power supply voltages, aswell as to increase the unity gain frequency of the corrected op-amp. However, such an intermediatestage is an essential non-linear link that limits the maximum output currents that recharge theop-amp correction capacitor. The results of computer simulation of two modifications of theAmpSR1, AmpSR2 op amps, which differ from each other in the structure of a nonlinear parallelchannel, which eliminates the dynamic overload of a "folded" cascode, are presented. The relevanceof the research performed is related to the problems of import substitution in the class ofhigh-speed op-amps and the lack of new and promising ideas for increasing the SR of the op-ampbased on the simultaneous use of non-linear and differentiating transient correction circuits in thelarge signal mode among analog circuit designers. The considered circuit techniques are alsoeffective when using CMOS technological processes.

On‐chip bias‐generating architecture for an automotive application with a wide input dynamic range

SummaryThis paper presents an on‐chip bias‐generating architecture for automotive applications with a wide input range of 3.8–36 V in a 0.18‐ m high‐voltage bipolar‐CMOS‐DMOS (BCD) process. The proposed architecture effectively manages high‐voltage stress issues with few high‐voltage devices optimizing the silicon area. The proposed bias‐generator comprising crude‐reference and crude‐regulator generates a preliminary low bias voltage for the bandgap‐reference circuit. An adaptive‐biased, with‐capacitor, low‐dropout regulator generates a well‐regulated core supply with low quiescent current and better stability over the wide input range. The adaptive biasing expands the unity gain frequency with increasing load enabling a fast‐transient response. The proposed LDO provides a 5‐V output voltage and a load current of 10 A to 20 mA from 5.5‐ to 36‐V supply with a 500‐mV dropout voltage consuming a very low quiescent current of 5 A. With 0‐ to 20‐mA load step and an output capacitor of 1 F, an undershoot of 40 mV and an overshoot of 55 mV are achieved.

Three-Stage Operational Amplifier with Frequency Compensation Using Cascade Zero

Short channel MOSFET exhibits the characteristics of wide bandwidth and low DC gain. A low DC gain causes a high gain error and a narrow output linear range in the closed loop. The DC gains can be improved by using the cascade structure, but frequency compensation is required due to the increase in the number of poles. The output nodes of each stage in a cascade Common-Source amplifier have a cascade of zero, and this zero is cancelled out by the input node of the next stage. This paper proposes a three-stage operational amplifier (op-amp) with frequency compensation using cascade zero. This op-amp was implemented in the 180 nm CMOS technology and achieved 86.96 MHz unity–gain frequency, 51.7° phase margin at 32 pF load capacitor and 99.83 dB DC gain, that is, a 36.21 dB improvement over a two-stage op-amp with the same power consumption. The op-amp consumed 7.74 mW with a supply voltage of 1.8 V.

A feed-forward compensated FVF LDO regulator with no on-chip compensation capacitors

This paper proposes a capacitor-free Flipped Voltage Follower (FVF) Low Dropout (LDO) regulator. To stabilize the feed-back loop, the proposed multi-stage FVF LDO regulator does not require a Miller compensation capacitor or physical resistor. A capacitor-free internal structure improves closed-loop bandwidth while saving area in the LDO regulator. In this work, a large feed-forward transconductor (gmf) is proposed, which generates a strong left-half-plane (LHP) zero while consuming a small bias current. The large feed-forward transconductor boosts the LDO regulator’s DC gain and bandwidth. The proposed FVF LDO regulator is implemented in standard 130nm CMOS technology and achieves a unity gain frequency of more than 35 MHz while consuming a total quiescent current of 97μA. The proposed FVF LDO regulator has an active area of 0.0054mm2, which is less than many other LDO regulators that have been reported.

Investigation of Temperature Dependence of mmWave Power Amplifier Large-Signal Reliability Performance

This work aims to study the temperature dependence on the long-term reliability of a power amplifier (PA) cell fabricated using 40-nm partially depleted-silicon on insulator (PD-SOI) nFET under dc and large-signal RF stress. Voltage swing caused by large RF signals complicates the stress mechanism due to frequent switching of stress from conducting to nonconducting. The impact of temperature on the time slope exponent ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${n}$ </tex-math></inline-formula> ) is also analyzed to understand the degradation mechanism at different temperatures. The values of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${n}$ </tex-math></inline-formula> are found to increase with the temperature pointing to the generation of new defects at the interface. A comparative reliability analysis is presented for dc, small-, and large-signal performance under varied accelerated dc and large-signal stress at drain and gate for different temperatures. Unity gain frequencies are also temperature sensitive and show high degradation at elevated temperatures. In our study, we have investigated the lifetime as a function of temperature of the PA operating in compression. It is observed that the lifetime is more than ten years when the PA operates at room temperature, which deteriorates as the measurement chuck temperature rises.

Straightforward bias- and frequency-dependent small-signal model extraction for single-layer graphene FETs

We propose an explicit small-signal graphene field-effect transistor (GFET) parameter extraction procedure based on a charge-based quasi-static model. The dependence of the small-signal parameters on both gate voltage and frequency is precisely validated by high-frequency (up to 18 GHz) on-wafer measurements from a 300 nm device. These parameters are studied simultaneously, in contrast to other works which focus exclusively on few. Efficient procedures have been applied to GFETs for the first time to remove contact and gate resistances from the Y-parameters. The use of these methods yields straightforward equations for extracting the small-signal model parameters, which is extremely useful for radio-frequency circuit design. Furthermore, we show for the first time experimental validation vs. both gate voltage and frequency of the intrinsic GFET non-reciprocal capacitance model. Accurate models are also presented for the gate voltage-dependence of the measured unity-gain and maximum oscillation frequencies as well as of the current and power gains.

Analysis and Measurements of an Urea Biosensor Based on Instrumentation Amplifier Chip With Cross-Coupled Technique

In this work, we design a high common-mode rejection ratio (CMRR) and low unity gain frequency (UGF) cross-coupled instrumentation amplifier (CCIA). This design was implemented by the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process technology. By using the three proposed cross-coupled operational amplifier, the CCIAs was designed with the power supply of +1.8 and −1.8 V. The instrumentation amplifier (IA) achieved a voltage gain of 56.92 dB with a CMRR of 126.08 dB. This IA was applied on an arrayed RuO2 urea biosensor as a readout circuit. Moreover, the sensing characteristics of the urea biosensor were analyzed. The experimental results show that our arrayed RuO2 urea biosensor combined with CCIA has a good average sensitivity of 2.933 mV/(mg/dL) and a linearity of 0.998. With the proposed IA, an effective measurement system can be achieved due to simplicity, convenience, and low cost.

Potentiometric Nonenzymatic Ascorbic Acid Sensor for Static and Dynamic Measurements

We fabricated a potentiometric nonenzymatic ascorbic acid (AA) sensor. The main sensing materials are molybdenum trioxide (MoO3) film and copper oxide nanoparticles (CuO NPs). Basic sensors and sensing materials were fabricated by the screen printing technique, the radio frequency sputtering system, and the green synthesis method. The average sensitivity, linearity, and interference effects of the AA sensor under static measurements were examined. In order to simulate dynamic measurements, we performed experiments by the microfluidic system and analyzed the best sensing characteristic at low flow rates (1.4– <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$7.0~\mu \text{L}$ </tex-math></inline-formula> /min) and high flow rates (10– <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$50~\mu \text{L}$ </tex-math></inline-formula> /min). The best average sensitivities under static and dynamic measurements are 35.26 and 61.11 mV/decade, respectively. Ultimately, the AA sensor achieves better stability and accuracy with the help of a unity-gain frequency and low power consumption instrumentation amplifier (UGFPCIA). This study shows that the AA sensor can possibly achieve excellent sensing properties even without the help of enzyme and a conventional commercial chip (LT1167).

Application of Non-Enzymatic Lactate Sensor Modified by Graphitic Carbon Nitride/Iron–Platinum Nanoparticles and Combined With the Low Power Consumption Instrumentation Amplifier and Calibration Readout Circuit

In a previous study, this laboratory produced and tested a lactic acid biosensor using a copper-doped zinc oxide (CZO) sensing film modified with graphite carbon nitride (g-C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> ) and iron platinum nanoparticles (FePt NPs). The previous sensor exhibited two non-ideal effects during persistent use and when alternating between high and low lactose concentrations. Using a low unity-gain frequency and low power consumption instrumentation amplifier (UGFPCIA) in conjunction with a calibration readout circuit, it was possible to reduce the previously observed drift and hysteresis effects. The UGFPCIA and calibration readout circuit were connected to a voltage-time (V-T) measurement system so the effects could be accurately quantified. The influence of the UGFPCIA on the measurement characteristics of the lactate biosensor were recorded and compared to a similar device using a commercial LT1167. Results showed that the UGFPCIA produced a more stable measurement, where linearity increased from 0.985 to 0.998. When measuring interference effects, the fluctuation in response voltage became smaller, and the time drift effect was successfully reduced by 89.7%. The hysteresis effect reduced the forward period by 0.13 mV, and the reverse period by 4.37 mV.

A 0.3V Rail-to-Rail Three-Stage OTA With High DC Gain and Improved Robustness to PVT Variations

This paper presents a novel 0.3V rail-to-rail body-driven three-stage operational transconductance amplifier (OTA). The proposed OTA architecture allows achieving high DC gain in spite of the bulk-driven input. This is due to the doubled body transconductance at the first and third stages, and to a high gain, gate-driven second stage. The bias current in each branch of the OTA is accurately set through gate-driven or bulk-driven current mirrors, thus guaranteeing an outstanding stability of main OTA performance parameters to PVT variations. In the first stage, the input signals drive the bulk terminals of both NMOS and PMOS transistors in a complementary fashion, allowing a rail-to-rail input common mode range (ICMR). The second stage is a gate-driven, complementary pseudo-differential stage with an high DC gain and a local CMFB. The third stage implements the differential-to-single-ended conversion through a body-driven complementary pseudo-differential pair and a gate-driven current mirror. Thanks to the adoption of two fully differential stages with common mode feedback (CMFB) loop, the common-mode rejection ratio (CMRR) in typical conditions is greatly improved with respect to other ultra-low-voltage (ULV) bulk-driven OTAs. The OTA has been fabricated in a commercial 130nm CMOS process from STMicroelectronics. Its area is about 0.002 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mm</i> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and power consumption is less than 35nW at the supply-voltage of 0.3V. With a load capacitance of 35pF, the OTA exhibits a DC gain and a unity-gain frequency of about 85dB and 10kHz, respectively.

A 50 dB high-gain operational amplifier integrated with metal-oxide TFTs

This paper presents a 50 dB high-gain operational amplifier (OPAMP), which is fabricated by unipolar n-type indium–zinc–oxide thin-film transistors. Different positive feedback technologies are employed to achieve sufficient voltage gain. The fabricated OPAMP exhibits an open-loop voltage gain (A v) of 50 dB over a −3 dB bandwidth of 15 kHz at the supply voltage of 20 V. The measured unity-gain frequency (f UG) and the DC power consumption are 500 kHz and 8.07 mW, respectively. In addition, an effective frequency compensation scheme is also introduced and simulated. The simulation results that the proposed OPAMP has a voltage gain of 50 dB with 60° phase margin at 150 kHz unity-gain frequency after compensation.

Design of Polymer-Based Trigate Nanoscale FinFET for the Implementation of Two-Stage Operational Amplifier

The major motivation behind transistor scaling is the requirement for high-speed transistors with lower fabrication costs. When the fin thickness or breadth is smaller than 10 nm in a trigate FET, charges travel in a nonconfined fashion, resulting in the creation of energy subbands and causing volume inversion. In comparison to the carrier near a surface inversion layer, volume inversion experiences less interface scattering. In large-scale integrations, we have focused on developing a 3D model for surface potential by establishing the three-dimensional Poison’s equation and building a unique fin field-effect transistor (FinFET) structure. In this context, there is a growing interest in developing a low-cost, simple solution that combines plastic (polymer) as a substrate and organic materials to create electronics such as monitors and sensors. The research examines characteristics such as silicon width, oxide thickness, doping concentration, metal work-function about gate, and various surface potentials. For different circuit configurations, it also examines the DC and AC characteristics of the FinFET structure. A differential amplifier is built for RF application based on the device specifications. This work is aimed at improving the semiconductor design structure by adjusting device parameters, analyzing the results, establishing the best FinFET device preferences, and selecting an application for the optimized device. The 3D Poisson’s equation may be used to create an analytical model of a trigate nanosize FinFET, which can then be tested using a TCAD simulator. By constructing such a FinFET, we can structure and analyze various electrostatic parameters. To facilitate the creation of FinFET-based circuits, including product development, a novel transistor needs a creative device basis. The infrastructure’s support denotes a computationally advantageous numerical model that accurately depicts a FinFET. The work presents a compact model for semiconductor manufacturing that permits separate IC productions while achieving higher levels of excellence and using less power. The design outperforms the CMOS by 22.7% in gain, 31.48% in power consumption, and 12.72% in CMRR, while operating at a 5 GHz unity gain frequency.