Unique Input Output Research Articles

Thalamic subnetworks as units of function.

The thalamus engages in various functions including sensory processing, attention, decision making and memory. Classically, this diversity of function has been attributed to the nuclear organization of the thalamus, with each nucleus performing a well-defined function. Here, we highlight recent studies that used state-of-the-art expression profiling, which have revealed gene expression gradients at the single-cell level within and across thalamic nuclei. These gradients, combined with anatomical tracing and physiological analyses, point to previously unappreciated heterogeneity and redefine thalamic units of function on the basis of unique input-output connectivity patterns and gene expression. We propose that thalamic subnetworks, defined by the intersection of genetics, connectivity and computation, provide a more appropriate level of functional description; this notion is supported by behavioral phenotypes resulting from appropriately tailored perturbations. We provide several examples of thalamic subnetworks and suggest how this new perspective may both propel progress in basic neuroscience and reveal unique targets with therapeutic potential.

$\mathcal k$-branching uio sequences for partially specified observable non-deterministic fsms

In black-box testing, test sequences may be constructed from systems modelled as deterministic finite-state machines (DFSMs) or, more generally, observable non-deterministic finite state machines (ONFSMs). Test sequences usually contain state identification sequences, with unique input output sequences ( <small>UIOs</small> ) often being used with DFSMs. This paper extends the notion of <small>UIOs</small> to ONFSMs. One challenge is that, as a result of non-determinism, the application of an input sequence can lead to exponentially many expected output sequences. To address this scalability problem, we introduce <inline-formula><tex-math notation="LaTeX">${\mathcal K}$</tex-math></inline-formula> - <small>UIOs</small> : <small>UIOs</small> that lead to at most <inline-formula><tex-math notation="LaTeX">${\mathcal K}$</tex-math></inline-formula> output sequences from states of <inline-formula><tex-math notation="LaTeX">$M$</tex-math></inline-formula> . We show that checking <inline-formula><tex-math notation="LaTeX">${\mathcal K}$</tex-math></inline-formula> - <small>UIO</small> existence is PSPACE-Complete if the problem is suitably bounded; otherwise it is in EXPSPACE and PSPACE-Hard. We provide a massively parallel algorithm for constructing <inline-formula><tex-math notation="LaTeX">${\mathcal K}$</tex-math></inline-formula> - <small>UIOs</small> and the results of experiments on randomly generated and real FSM specifications. The proposed algorithm was able to construct <small>UIOs</small> in cases where the existing <small>UIO</small> generation algorithm could not and was able to construct <small>UIOs</small> from FSMs with 38K states and 400K transitions.

Oracles for Testing Software Timeliness with Uncertainty

Uncertainty in timing properties (e.g., detection time of external events) is a common occurrence in embedded software systems, since these systems interact with complex physical environments. Such time uncertainty leads to non-determinism. For example, time-triggered operations may either generate different valid outputs across different executions or experience failures (e.g., results not being generated in the expected time window) that occur only occasionally over many executions. For these reasons, time uncertainty makes the generation of effective test oracles for timing requirements a challenging task. To address the above challenge, we propose Stochastic Testing with Unique Input Output Sequences, an approach for the automated generation of stochastic oracles that verify the capability of a software system to fulfill timing constraints in the presence of time uncertainty. Such stochastic oracles entail the statistical analysis of repeated test case executions based on test output probabilities predicted by means of statistical model checking. Results from two industrial case studies in the automotive domain demonstrate that this approach improves the fault detection effectiveness of tests suites derived from timed automata compared to traditional approaches.

Test Sequence Reduction of Wireless Protocol Conformance Testing to Internet of Things

Wireless communication protocols are indispensable in Internet of Things (IoT), which refer to rules and conventions that must be followed by both entities to complete wireless communication or service. Wireless protocol conformance testing concerns an effective way to judge whether a wireless protocol is carried out as expected. Starting from existing test sequence generation methods in conformance testing, an improved method based on overlapping by invertibility and multiple unique input/output (UIO) sequences is proposed in this paper. The method is accomplished in two steps: first, maximum-length invertibility-dependent overlapping sequences (IDOSs) are constructed, then a minimum-length rural postman tour covering the just constructed set of maximum-length IDOSs is generated and a test sequence is extracted from the tour. The soundness and effectiveness of the method are analyzed. Theory and experiment show that desirable test sequences can be yielded by the proposed method to reveal violations of wireless communication protocols in IoT.

Parallel Algorithms for Testing Finite State Machines:Generating UIO Sequences

This paper describes an efficient parallel algorithm that uses many-core GPUs for automatically deriving Unique Input Output sequences (UIOs) from Finite State Machines. The proposed algorithm uses the global scope of the GPU's global memory through coalesced memory access and minimises the transfer between CPU and GPU memory. The results of experiments indicate that the proposed method yields considerably better results compared to a single core UIO construction algorithm. Our algorithm is scalable and when multiple GPUs are added into the system the approach can handle FSMs whose size is larger than the memory available on a single GPU.

The potential for reducing China's carbon dioxide emissions: Role of foreign-invested enterprises

In this paper, we discuss the possible role of foreign-invested enterprises in the reduction of China's carbon dioxide emissions by employing a time-series of unique input–output tables that distinguishes firm ownership and processing exports. The comparisons of carbon emission intensities indicate that although Chinese-owned enterprises experienced much faster upgrades of emission-intensity-related technologies since 1992, foreign-invested enterprises continued to outperform Chinese-owned enterprises by 10–110% in terms of sectoral emission intensities until 2010. Therefore, China may have reduced its carbon dioxide emissions by 1200–1400 million tonnes during 1992–2010, if Chinese-owned enterprises could have duplicated the emission-intensity-related technologies of the corresponding foreign-invested enterprises. More specifically, China should prioritize the adoption of the thermal and wind power generation technologies of the U.S., the photovoltaic system and related national electric grid upgrading technologies of Germany, the mineral and metal production and carbon emissions control technologies of Japan, and the machinery and transportation technologies of Europe. In an ideal scenario that assumes Chinese-owned enterprises would have eventually adopted the world's leading technologies, China could have reduced its total carbon dioxide emissions by about 50% in 2010. From a policy perspective, as foreign-invested enterprises are quite widespread; they can serve as very effective and efficient channels for technology transfer from developed to developing countries.

The energy efficiency advantage of foreign-invested enterprises in China and the role of structural differences

In this paper, we use a unique input–output table that distinguishes trade mode and firm ownership to discuss the relative advantage of foreign-invested enterprises (FIEs) in Mainland China. It is found that FIEs outperform Chinese owned enterprises (COEs) in terms of total energy intensity by 16.97%, 14.97% and 42.89%, respectively, for the processing, non-processing and overall production in the industrial sector. Further decompositions show that structural differences across industries (and trade mode) contribute positively and account for 65.33%, 26.28% and 81.93% of the relative advantage of FIEs for processing, non-processing and overall production. Failure to capture heterogeneity across trade mode may lead to distortion of the picture of how final demand structure differences influence the energy efficiency advantage of FIEs over COEs in China.

A hybrid optimization approach to conformance testing of finite automata

Unique Input–Output sequences (UIOs) are quite commonly used in conformance testing. Unfortunately finding UIOs of minimal length is an NP hard problem. This study presents a hybrid approach to generate UIOs automatically on a basis of the finite state machine (FSM) specification. The proposed hybrid approach harnesses the benefits of hill climbing (Greedy search) and heuristic algorithm. Hill climbing, which exploits domain knowledge, is capable of quickly generating good result however it may get stuck in local minimum. To overcome the problem we used a set of parameters called the seed, which allows the algorithm to generate different results for a different seed. The hill climbing generates solutions implied by the seed while the Genetic Algorithm is used as the seed generator. We compared the hybrid approach with Genetic Algorithm, Simulated Annealing, Greedy Algorithm, and Random Search. The experimental evaluation shows that the proposed hybrid approach outperforms other methods. More specifically, we showed that Genetic Algorithm and Simulated Annealing exhibit similar performance while both of them outperform Greedy Algorithm. Finally, we generalize the proposed hybrid approach to seed-driven hybrid architectures and elaborate on how it can be adopted to a broad range of optimization problems.

An efficient approach to design a reversible control unit of a processor

Reversible logic has captured significant attention in recent time as reducing power consumption is one of the main concern of digital logic design. It consumes less power by recovering bit loss from its unique input–output mapping. In this paper, we propose a reversible control unit, which is first ever proposed in literature. Two new 4×4 reversible gates, namely HL gate and BJ gate, are proposed to design reversible decoder and J-K flip-flop. An algorithm has been shown to design a reversible control unit. On the way to design the control unit, we propose reversible decoder, sequence counter, instruction register and control logic gates. These circuits are analyzed with the existing ones. The comparative results show that the proposed design outperforms the existing designs in terms of numbers of gates, garbage outputs, delay and quantum cost. In addition, some lower bounds on the numbers of gates and garbage outputs of the proposed control unit have also been presented.

FINANCIAL DISTRESS AND INDUSTRY STRUCTURE: AN INTER-INDUSTRY APPROACH TO THE LOST DECADE IN JAPAN

This paper proposes a novel approach to investigating the propagation mechanism of balance sheet deterioration in financial institutions and firms, by extending the input–output analysis. First, we use a unique input–output table augmented by firm size dimension. Second, we link the input–output table with the balance sheet conditions of financial institutions and firms. Based on Japanese input–output tables, we find that the lending attitude of financial institutions affected firms’ input decision in the late 1990s and the early 2000s. Simulation exercises are conducted to evaluate the effects of changes in the lending attitude toward small firms as favorable as that toward large firms on sectoral allocations. We find that output was increased for small firms and reduced for large firms. The change in output was non-negligible, about 5.5% of the initial output of each sector. In particular, it exceeded 20% in textile, iron and steel and fabricated metal products.

A study on the extended unique input/output sequence

The unique input/output (UIO) sequence is an important state identification technique in the FSM-based protocol conformance testing. However, some states of a FSM might have no UIO sequence. To address the above problem, this paper introduces an extended UIO sequence, called a GUIO sequence, which distinguishes a designated state from the remaining states by a group-by-group means. The problem of searching the optimal GUIO sequence is NP-hard. In this paper, we present a GUIO search method based on a greedy heuristics and a φ-hop search approach. The proposed method can obtain desirable GUIO sequences with relatively low computational complexity.

Crossover can be constructive when computing unique input–output sequences

Unique input–output (UIO) sequences have important applications in conformance testing of finite state machines (FSMs). Previous experimental and theoretical research has shown that evolutionary algorithms (EAs) can compute UIOs efficiently on many FSM instance classes, but fail on others. However, it has been unclear how and to what degree EA parameter settings influence the runtime on the UIO problem. This paper investigates the choice of acceptance criterion in the (1 + 1) EA and the use of crossover in the $$(\mu+1)$$ Steady State Genetic Algorithm. It is rigorously proved that changing these parameters can reduce the runtime from exponential to polynomial for some instance classes of the UIO problem.

Guest Editorial: special issue on evolutionary optimisation and learning

Problem-solving techniques based on simulated evolution, particularly those inspired by the Darwinian theory of natural selection and biological evolution, have attracted great attention. These evolutionary optimisation and learning algorithms differ from the traditional optimisation and learning methods in that they involve a search from a population of solutions. Over the past decades, evolutionary optimisation and learning algorithms have been successfully applied to a wide variety of real-world problems. This special issue brings together some recent works from a wide range of topics concerning evolutionary optimisation and learning, including Differential Evolution, Cellular Genetic Algorithms, Particle Swarm Optimisation, Artificial Immune System, Coevolution, Crossover Analysis, Dynamic Combinatorial Optimisation, and Multimodal Optimisation. The eight papers included in this special issue originated from SEAL’08 (7th International Conference on Simulated Evolution and Learning), but have been substantially extended and revised from the conference version. These further extended papers were again rigorously reviewed in two rounds by at least three anonymous reviewers. The paper by Lehre and Yao investigates the impact of the parameter settings particularly the acceptance criterion in evolutionary algorithms (EAs) and the crossover operator SSGA when computing unique input output sequences (UIOs) from finite state machines. The objective is to identify simple, archetypical cases where these EA parameter settings have a particularly strong effect on the runtime of the algorithm. This result shows that minor modification in evolutionary algorithms can have an exponentially large runtime impact for computing UIOs and that when computing UIOs, the crossover operator can be essential, and simple EAs can be inefficient. The paper by Ronkknen et al. describes a software framework for generating multimodal test functions. The framework provides an easy way to construct parameterisable functions and offers an environment for testing multimodal optimisation algorithms. A number of function families with different characteristics are included. The framework implements new parameterisable function families for generating desired landscapes. In addition, the framework implements a selection of well-known test functions from the literature, which can be rotated and stretched. The software module can be easily imported into any optimisation algorithm implementation compatible with the C-programming language. As an example, eight optimisation approaches are compared by their ability to locate several global optima over a set of 16 functions with different properties generated by the proposed module. The paper by Dick and Whigham introduces two modifications to the local sharing method for multimodal optimisation. The first alters local sharing so that parent selection and fitness sharing operate at two different spatial levels: parent selection is performed within small demes, M. Zhang (&) School of Engineering and Computer Science, Victoria University of Wellington, PO Box 600, Wellington, New Zealand e-mail: mengjie.zhang@ecs.vuw.ac.nz

Runtime analysis of the (1 + 1) EA on computing unique input output sequences

Computing unique input output (UIO) sequences is a fundamental and hard problem in conformance testing of finite state machines (FSM). Previous experimental research has shown that evolutionary algorithms (EAs) can be applied successfully to find UIOs for some FSMs. However, before EAs can be recommended as a practical technique for computing UIOs, it is necessary to better understand the potential and limitations of these algorithms on this problem. In particular, more research is needed in determining for what instance classes of the problem EAs are feasible, and for what instance classes EAs are provably better than random search strategies.This paper presents rigorous theoretical and numerical analyses of the runtime of the (1+1) EA and random search on several selected instance classes of this problem. The theoretical analysis shows firstly, that there are instance classes where the EA is efficient, while random testing fails completely. Secondly, an instance class that is difficult for both random testing and the EA is presented. Finally, a parametrised instance class with tunable difficulty is presented. The numerical study estimates the constants in the asymptotic expressions obtained in the theoretical analysis, and the variability of the runtime. The numerical results fit well with the theoretical results, even for small problem instance sizes. Together, these results provide a first theoretical characterisation of the potential and limitations of the (1+1) EA on the problem of computing UIOs.

Evolutionary generation of unique input/output sequences for class behavioral testing

Object-oriented software is composed of classes. Their behaviors are usually modeled with state diagrams or finite state machines (FSMs). Testing classes is regarded as testing FSMs in which unique input/output (UIO) sequences are widely applied. The generation of UIO sequences is shown to be an undecidable problem. For these problems, genetic algorithms (GAs) may offer much promise. This paper reports some primary results of on-going research on evolutionary testing classes. First, we explain how to define UIO sequence generation as a search problem, and then describe adapting genetic algorithms to generating UIO sequences. Special issues of using genetic algorithms such as solution representation, validity checking and fitness definition are discussed in detail. Primary experiments confirm the applicability and feasibility of applying GAs to UIO sequence generation.

Synthesis of finite state machines for improved state verification

Finite State Machines (FSMs) are used in diverse areas to model hardware and software systems. Verification of FSMs is essential to ensure reliability of systems. To verify that a machine is in an expected state in testing, Unique Input/Output (UIO) sequences are used. The aforementioned testing methodology requires that each state in the FSM has an UIO. However, it is possible for a given machine that few or even none of its states have an UIO sequence. This paper presents a guided heuristic algorithm for synthesizing FSMs such that each state has an UIO sequence. The states of an FSM with identical I/O labels on transitions are grouped in order to identify the states which do not possess UIO sequence. The transitions are then augmented by adding extra output terminals incrementally so that new UIO sequences are created for the states. A greedy approach is used to optimize the number of added outputs. Initially, the transitions which lead to state convergence (i.e., transitions with identical input/output labels taking a set of states to the same next state) and constrained self-loop (i.e., transitions taking a set of states either to itself or leads to state convergence) are identified since a state with only these transitions will never have a UIO sequence. Extra output terminals are added to the FSM which are used only while testing and the augmented output labels make sure that the states are neither convergent nor has constrained self-loop, thereby ensuring UIO sequence. The proposed algorithm, referred to as AUGP, was tested with a large number of FSMs including the Microelectronics Center of North Carolina (MCNC) FSM benchmarks. The augmented state transition table was used as input to a UIO computation algorithm (developed by the same authors [Ahmad I, et al. IEE Proc Comput Digital Tech 2004;151(2):131]) to check the performance of the augmentation algorithm and the tested FSMs were found to possess UIO sequence for all states.

Automated Unique Input Output Sequence Generation for Conformance Testing of FSMs

This paper describes a method for automatically generating unique input output (UIO) sequences for FSM conformance testing. UIOs are used in conformance testing to verify the end state of a transition sequence. UIO sequence generation is represented as a search problem and genetic algorithms are used to search this space. Empirical evidence indicates that the proposed method yields considerably better (up to 62% better) results compared with random UIO sequence generation.

Improving test quality using robust unique input/output circuit sequences (UIOCs)

In finite state machine (FSM) based testing, the problem of fault masking in the unique input/output (UIO) sequence may degrade the test performance of the UIO based methods. This paper investigates this problem and proposes the use of a new type of unique input/output circuit (UIOC) sequence for state verification, which may help to overcome the drawbacks that exist in the UIO based techniques. When constructing a UIOC, overlap and internal state observation schema are used to increase the robustness of a test sequence. Test quality is compared by using the forward UIO method (F-method), the backward UIO method (B-method) and the UIOC method (C-method) separately. Robustness of the UIOCs constructed by the algorithm given in this paper is also compared with those constructed by the algorithm given previously. Experimental results suggest that the C-method outperforms the F- and the B-methods and the UIOCs constructed by the algorithm given in this paper, are more robust than those constructed by other proposed algorithms.

LANG – algorithm for constructing unique input/output sequences in finite-state machines

Finite-state-machines (FSMs) model a variety of hardware and software systems. Unique input/output (UIO) sequences are used in generation of test sequences to verify that a machine is in an expected state, which in turn ensures system reliability. The paper presents an efficient algorithm for computing UIO sequences for completely and incompletely specified FSMs with binary inputs. Set of states which produces identical outputs for nonconflicting inputs are partitioned by incrementally constructing a successor tree. The transitions of FSM are modified to create a set of more specified transitions. This also resulted in constructing UIO sequences for an additional number of states. By a heuristic breadth-first search of successor tree, shorter test sequences are generated. In addition, classifying the nodes as ‘active’, ‘inactive’ and ‘dead’ and application of pruning rules and termination checks applied while partitioning the states reduced the search space and speeded up UIO-sequence construction. A chain-node search technique was used when successor tree failed to construct UIO sequences in some FSMs. The proposed algorithm, designated LANG, was tested with a large number of FSMs including the MCNC FSM benchmarks. To show the effectiveness of the proposed algorithm, results are compared with existing UIO-sequence-computation algorithms. The proposed algorithm computed shorter UIO sequences in negligible CPU time.

Test generation for sequential circuits using state transition diagram and test generation for combinatorial circuit part

AbstractThis study deals with single stuck‐at faults in sequential circuits; in particular, a test generation method featuring low generation complexity and short test sequences. With the proposed method, short test sequences are generated using shortest local connections between activation vector set found for combinatorial circuit part at gate level, and state transitions found from state transition diagram at functional level. Generated test sequences are input sequences composed of subsequences referred to as single test sequences. Single test sequences are composed of state control sequences that control activation vectors and their states, and UIO (Unique Input/Output) sequences that confirm states after applying activation vectors. Test sequences are generated so as to locally minimize total length of state control sequences and UIO sequences in connected single test sequences, which results in shorter test sequences as compared to previous generation methods. Evaluation experiments using MCNC benchmarks proved that test sequences generated by the proposed method were shorter by up to 28.8% as compared to previous methods while fault coverage was above 98% on the average. © 2001 Scripta Technica, Electron Comm Jpn Pt 2, 84(8): 20–28, 2001