Underlying Hardware Architecture Research Articles

FortiFix : A Fault Attack Aware Compiler Framework for Crypto Implementations

Fault attacks are one of the most powerful forms of cryptanalytic attack on embedded systems, that can corrupt cipher’s operations leading to a breach of confidentiality and integrity. A single precisely injected fault during the execution of a cipher can be exploited to retrieve the secret key in a few milliseconds. Naïve countermeasures introduced into implementation can lead to huge overheads, making them unusable in resource-constraint environments. On the other hand, optimized countermeasures requires significant knowledge, not just about the attack, but also on the (a) the cryptographic properties of the cipher, (b) the program structure, and (c) the underlying hardware architecture. This makes the protection against fault attacks tedious and error-prone. In this paper, we introduce the first automated compiler framework named FortiFix that can detect and patch fault exploitable regions in a block cipher implementation. The framework has two phases. The pre-compilation phase identifies regions in the source code of a block cipher that are vulnerable to fault attacks. The second phase is incorporated as transformation passes in the LLVM compiler to find exploitable instructions, quantify the impact of a fault on these instructions, and finally insert appropriate countermeasures based on user defined security requirements. As a proof of concept, we have evaluated two block cipher implementations AES-128 and CLEFIA-128 on three different hardware platforms such as MSP430 (16-bit), ARM (32-bit) and RISCV (32-bit).

Experimental demonstration of multiparty quantum secret sharing and conference key agreement

Quantum secret sharing (QSS) and conference key agreement (CKA) provide efficient encryption approaches for realizing multi-party secure communication, which are essential components of quantum networks. In this work, a practical, scalable, verifiable (k, n) threshold continuous variable QSS protocol secure against eavesdroppers and dishonest players are proposed and demonstrated. The protocol does not require preparing the laser source by each player and phase locking of independent lasers. The parameter evaluation and key extraction can be accomplished by only the dealer and the corresponding player. By using the multiple sideband modulation, a single heterodyne detector can extract the information of multiple players. The practical security of the system is considered. The system is versatile, it can support the CKA protocol by only modifying the classic post-processing and requiring no changes to the underlying hardware architecture. By implementing the QSS and CKA protocols with five parties over 25 km (55 km) single-mode fibers, a key rate of 0.0061 (7.14 × 10−4) bits per pulse is observed. The results significantly reduces the system complexity and paves the way for the practical applications of QSS and CKA with efficient utilization of resources and telecom technologies.

Reducing the CNOT Count for Clifford+T Circuits on NISQ Architectures

While mapping a quantum circuit to the physical layer one has to consider the numerous constraints imposed by the underlying hardware architecture. Connectivity of the physical qubits is one such constraint that restricts two-qubit operations, such as CNOT, to "connected" qubits. SWAP gates can be used to place the logical qubits on admissible physical qubits, but they entail a significant increase in CNOT-count. In this paper we consider the problem of reducing the CNOT-count in Clifford+T circuits on connectivity constrained architectures, like noisy intermediate-scale quantum (NISQ) computing devices. We "slice" the circuit at the position of Hadamard gates and "build" the intermediate {CNOT,T} sub-circuits using Steiner trees, significantly improving on previous methods. We compared the performance of our algorithms while mapping different benchmark and random circuits to some well-known architectures such as 9-qubit square grid, 16-qubit square grid, Rigetti 16-qubit Aspen, 16-qubit IBM QX5 and 20-qubit IBM Tokyo. Our methods give less CNOT-count compared to Qiskit and TKET transpiler as well as using SWAP gates. Assuming most of the errors in a NISQ circuit implementation are due to CNOT errors, then our method would allow circuits with few times more CNOT gates be reliably implemented than the previous methods would permit.

FaultMeter: Quantitative Fault Attack Assessment of Block Cipher Software

Fault attacks are a potent class of physical attacks that exploit a fault njected during device operation to steal secret keys from a cryptographic device. The success of a fault attack depends intricately on (a) the cryptographic properties of the cipher, (b) the program structure, and (c) the underlying hardware architecture. While there are several tools that automate the process of fault attack evaluation, none of them consider all three influencing aspects.This paper proposes a framework called FaultMeter that builds on the state-of-art by not just identifying fault vulnerable locations in a block cipher software, but also providing a quantification for each vulnerable location. The quantification provides a probability that an injected fault can be successfully exploited. It takes into consideration the cryptographic properties of the cipher, structure of the implementation, and the underlying Instruction Set Architecture’s (ISA) susceptibility to faults. We demonstrate an application of FaultMeter to automatically insert optimal amounts of countermeasures in a program to meet the user’s security requirements while minimizing overheads. We demonstrate the versatility of the FaultMeter framework by evaluating five cipher implementations on multiple hardware platforms, namely, ARM (32 and 64 bit), RISC-V (32 and 64 bit), TI MSP-430 (16-bit) and Intel x86 (64-bit).

Genetic algorithm enabled virtual multicast tree embedding in Software-Defined Networks

The recent network virtualization technology enables the multi-tenancy, where various virtual network requests can share the same physical network by decoupling network services from the underlying hardware architecture. The process of virtual node and link mapping onto a shared Substrate Network (SN) by satisfying the requested network resources (i.e., bandwidth, computing capacity, etc.) is referred to as Virtual Network Embedding (VNE), which is known as an NP-Hard problem. The problem of VNE aims to exhibit one-to-one (unicast) communication. However, the motivation of this research is to explore how to efficiently map virtual networks with one-to-many (multicast) communications, which are in the form of Virtual Multicast Trees (VMTs), onto an SN. This problem differs from the traditional VNE problem and has not been well-studied by the research community. To this end, we propose a novel algorithm, Modified Genetic Algorithm for Virtual Multicast Tree Embedding (MGA-VMTE), to embed VMTs onto a shared SN in this research. The proposed MGA-VMTE algorithm focuses on minimizing the network resource consumption (i.e., bandwidth) under end-to-end delay constraint in the SN while satisfying the computing request of virtual nodes. Our extensive simulations demonstrate that the MGA-VMTE algorithm outperforms the dynamic impact factor and traditional greedy-based virtual multicast tree embedding approaches regarding bandwidth consumption, acceptance ratio, and resource depletion ratio metrics on NSFNET, USNET, Random-60 node, and Random-120 node network topologies.

A Simulation Scheduling Module to Improve User Experience in the Simugan Beef-Cattle Farm Simulator

At the Faculty of Veterinary Sciences of the National University of Central Buenos Aires a client-server Beef-Cattle Farm simulator called Simugan has been developed. Simugan allows users to experiment over a virtual farm in a simple and low cost way compared with real farm conditions. Users can submit single simulation scenarios or multiple simulation scenarios packaged in an experimentation, where each scenario is a complete farm configuration. This is a key feature important in farm research, but with the drawback that some users might experiment long wait times for simulation results because of the amount of simulations the underlying hardware architecture has to process. Consequently, an heuristic scheduler module was added to Simugan producing a more equitative use of computer resources and an improvement of 41 % in users flow time, a popular metric to quantify how much time user simulations spend in the back end and hence a way of measuring deviations in users waiting times.

Model checking reveals design issues leading to spurious actuation of nuclear instrumentation and control systems

A spurious actuation of an industrial instrumentation and control (I&C) system is a failure mode where the system or its component inadvertently produces an operation without a justified reason to do so. Design issues leading to spurious failures are difficult to analyse, but pose a high risk for safety. Model checking is a formal verification method that can be used for exhaustive analysis of I&C systems. In this paper, we explain how formal properties that address spurious failures can be specified, and how model checking can then be used to verify I&C application logic designs based on vendor-specific function block diagrams. Based on over ten years of successful practical projects in the Finnish nuclear industry, we present 21 real-world design issues (representing 37% of all detected issues), each involving a systemic failure that could lead to spurious actuation of nuclear safety I&C. We then describe how random failures of the underlying hardware architecture—another cause for spurious actuation—can also be included in the models. With an experimental evaluation based on real-world nuclear industry models, we demonstrate that our method can be effectively used for the verification of single failure tolerance.

Architecture of embedded intelligent video analysis system for forest fire prevention

Forest fire has always been an important hidden danger in forestry management. It is necessary to monitor and manage forest fire through video monitoring system. However, due to the lack of real-time performance of traditional video monitoring system and the difficulty in data processing, an embedded intelligent video analysis system is designed. The system uses a software and hardware design method based on Zynq SoC, first, each functional module of the hardware architecture is divided, then the system software is designed, and finally the system is evaluated as a whole. Based on the application requirements of forest fire prevention, this paper focuses on the detailed description of the underlying hardware architecture and operating system software design, and provides some value and reference for the application scenarios of forest fire prevention.

Cluster Pruning: An Efficient Filter Pruning Method for Edge AI Vision Applications

Even though the Convolutional Neural Networks (CNN) has shown superior results in the field of computer vision, it is still a challenging task to implement computer vision algorithms in real-time at the edge, especially using a low-cost IoT device due to high memory consumption and computation complexities in a CNN. Network compression methodologies such as weight pruning, filter pruning, and quantization are used to overcome the above mentioned problem. Even though filter pruning methodology has shown better performances compared to other techniques, irregularity of the number of filters pruned across different layers of a CNN might not comply with majority of the neural computing hardware architectures. In this paper, a novel greedy approach called cluster pruning has been proposed, which provides a structured way of removing filters in a CNN by considering the importance of filters and the underlying hardware architecture. The proposed methodology is compared with the conventional filter pruning algorithm on Pascal-VOC open dataset, and Head-Counting dataset, which is our own dataset developed to detect and count people entering a room. We benchmark our proposed method on three hardware architectures, namely CPU, GPU, and Intel Movidius Neural Computer Stick (NCS) using the popular SSD-MobileNet and SSD-SqueezeNet neural network architectures used for edge-AI vision applications. Results demonstrate that our method outperforms the conventional filter pruning methodology, using both datasets on above mentioned hardware architectures. Furthermore, a low cost IoT hardware setup consisting of an Intel Movidius-NCS is proposed to deploy an edge-AI application using our proposed pruning methodology.

Towards Digital Twins for the Description of Automotive Software Systems

We present models for automotive software that capture quantitative and qualitative aspects of software systems and the underlying hardware architecture. In particular, we consider different levels of computing power. These range from controllers up to the cloud. We present a modeling approach for software deployment taking different automotive requirements such as criticality, latency, memory, computational resources, and communication into account. Our models capture automotive software and hardware system configurations and can serve as digital twins that are digital counterparts of (usually) physical entities. Furthermore, we highlight connected research areas and challenges.

GenSyth: a new way to understand deep learning

GenSyth: a new way to understand deep learning

Survey of deployment locations and underlying hardware architectures for contemporary deep neural networks

This article overviews the emerging use of deep neural networks in data analytics and explores which type of underlying hardware and architectural approach is best used in various deployment locations when implementing deep neural networks. The locations which are discussed are in the cloud, fog, and dew computing (dew computing is performed by end devices). Covered architectural approaches include multicore processors (central processing unit), manycore processors (graphics processing unit), field programmable gate arrays, and application-specific integrated circuits. The proposed classification in this article divides the existing solutions into 12 different categories, organized in two dimensions. The proposed classification allows a comparison of existing architectures, which are predominantly cloud-based, and anticipated future architectures, which are expected to be hybrid cloud-fog-dew architectures for applications in Internet of Things and Wireless Sensor Networks. Researchers interested in studying trade-offs among data processing bandwidth, data processing latency, and processing power consumption would benefit from the classification made in this article.

A formal model of data access for multicore architectures with multilevel caches

The performance of software running on parallel or distributed architectures can be severely affected by the location of data. In shared memory multicore architectures, data movement between caches and main memory is driven by data accesses from tasks executing in parallel on different cores and by a protocol to ensure cache coherence. This paper integrates cache coherence in a formal model of data access, to capture such data movement from an application perspective. We develop an executable model which captures cache coherent data movement between different cache levels and main memory, for software described by task-level data access patterns. The proposed model is generic in the number of cache levels and cores, and abstracts from the concrete communication medium. We show that the model guarantees expected correctness properties for cache coherence, in particular data consistency. This paper further presents a proof-of-concept implementation of the proposed model in rewriting logic, which allows different choices for the underlying hardware architecture of dynamically created parallel data access patterns to be specified and compared at the modelling level. • A formal, operational model of data access in multicore architectures with multilevel caches. • Correctness properties of the formal model, expressed as invariants over an arbitrary number of cores and caches. • A proof-of-concept implementation of the model to compare executions based on penalties, an abstract performance indicator.

Portable multi- and many-core performance for finite-difference or finite-element codes – application to the free-surface component of NEMO (NEMOLite2D 1.0)

Abstract. We present an approach which we call PSyKAl that is designed to achieve portable performance for parallel finite-difference, finite-volume, and finite-element earth-system models. In PSyKAl the code related to the underlying science is formally separated from code related to parallelization and single-core optimizations. This separation of concerns allows scientists to code their science independently of the underlying hardware architecture and for optimization specialists to be able to tailor the code for a particular machine, independently of the science code. We have taken the free-surface part of the NEMO ocean model and created a new shallow-water model named NEMOLite2D. In doing this we have a code which is of a manageable size and yet which incorporates elements of full ocean models (input/output, boundary conditions, etc.). We have then manually constructed a PSyKAl version of this code and investigated the transformations that must be applied to the middle, PSy, layer in order to achieve good performance, both serial and parallel. We have produced versions of the PSy layer parallelized with both OpenMP and OpenACC; in both cases we were able to leave the natural-science parts of the code unchanged while achieving good performance on both multi-core CPUs and GPUs. In quantifying whether or not the obtained performance is “good” we also consider the limitations of the basic roofline model and improve on it by generating kernel-specific CPU ceilings.

Topology-Aware Mapping Techniques for Heterogeneous HPC Systems: A Systematic Survey

At the present time, the modern platforms of high-performance computing (HPC) consists of heterogeneous computing devices which are connected through complex hierarchical networks. Moreover, it is moving towards the Exascale era and which makes the number of nodes to increase as well as the number of cores within a node to increase. As a consequence, the communication costs and the data movement are increasing. Given that, the efficient topology-aware process mapping has become vital to efficiently optimize the data locality management in order to improve the system performance and energy consumption. It will also decrease the communication cost of the processes by matching the application virtual topology (exploited by the system for assigning the processes to the physical processor) to the target underlying hardware architecture called physical topology. Additionally, improving the locality problem which is one of the most challenging issues faced by the current parallel applications. In this survey paper, we have studied various topology-aware mapping techniques and algorithms.

OpenDwarfs: Characterization of Dwarf-Based Benchmarks on Fixed and Reconfigurable Architectures

The proliferation of heterogeneous computing platforms presents the parallel computing community with new challenges. One such challenge entails evaluating the efficacy of such parallel architectures and identifying the architectural innovations that ultimately benefit applications. To address this challenge, we need benchmarks that capture the execution patterns (i.e., dwarfs or motifs) of applications, both present and future, in order to guide future hardware design. Furthermore, we desire a common programming model for the benchmarks that facilitates code portability across a wide variety of different processors (e.g., CPU, APU, GPU, FPGA, DSP) and computing environments (e.g., embedded, mobile, desktop, server). As such, we present the latest release of OpenDwarfs, a benchmark suite that currently realizes the Berkeley dwarfs in OpenCL, a vendor-agnostic and open-standard computing language for parallel computing. Using OpenDwarfs, we characterize a diverse set of modern fixed and reconfigurable parallel platforms: multi-core CPUs, discrete and integrated GPUs, Intel Xeon Phi co-processor, as well as a FPGA. We describe the computation and communication patterns exposed by a representative set of dwarfs, obtain relevant profiling data and execution information, and draw conclusions that highlight the complex interplay between dwarfs’ patterns and the underlying hardware architecture of modern parallel platforms.

Improving main memory hash joins on Intel Xeon Phi processors

Modern processor technologies have driven new designs and implementations in main-memory hash joins. Recently, Intel Many Integrated Core (MIC) co-processors (commonly known as Xeon Phi) embrace emerging x86 single-chip many-core techniques. Compared with contemporary multi-core CPUs, Xeon Phi has quite different architectural features: wider SIMD instructions, many cores and hardware contexts, as well as lower-frequency in-order cores. In this paper, we experimentally revisit the state-of-the-art hash join algorithms on Xeon Phi co-processors. In particular, we study two camps of hash join algorithms: hardware-conscious ones that advocate careful tailoring of the join algorithms to underlying hardware architectures and hardware-oblivious ones that omit such careful tailoring. For each camp, we study the impact of architectural features and software optimizations on Xeon Phi in comparison with results on multi-core CPUs. Our experiments show two major findings on Xeon Phi, which are quantitatively different from those on multi-core CPUs. First, the impact of architectural features and software optimizations has quite different behavior on Xeon Phi in comparison with those on the CPU, which calls for new optimization and tuning on Xeon Phi. Second, hardware oblivious algorithms can outperform hardware conscious algorithms on a wide parameter window. These two findings further shed light on the design and implementation of query processing on new-generation single-chip many-core technologies.

Android Based Energy Aware Framework for Porting Legacy Applications

Trend is growing towards using complex multimedia functions on smaller devices. In this study, we explore the effect of migrating legacy signal processing software applications algorithms from large form factor devices to the smaller one such as handheld mobile devices known as Energy Conscious Mobile Computing Systems (EConMCS). We concentrate on Source Code Volatility (SCV), including inherent algorithm complexity and the developer implementation. We identify code Transformation Steering Factors (TSF), such as loop unrolling factor, decision tree grafting factor and their relation to SCV. The impact of TSF is discussed for different multimedia applications in native Digital Signal Processor (DSP) compiler optimization while switching between different transformation schemes. Our results show that SCV can be minimized by using an architecture-centric algorithm that both enables the effective use of underlying hardware architectures and the memory access required to optimize energy consumption. The coded spatial access is implicitly dependent on layout, content and location of options and legibility that relates to a developer’s implementation of loops, code blocks and decision trees. The compiler-centric transformation model minimizes the effect of legacy code migration for multimedia applications. Results are exposed for the transformation of typical DSP applications and a video transcodec MPEG-4.

Finite-difference staggered grids in GPUs for anisotropic elastic wave propagation simulation

The 3D elastic wave equations can be used to simulate the physics of waves traveling through the Earth more precisely than acoustic approximations. However, this improvement in quality has a counterpart in the cost of the numerical scheme. A possible strategy to mitigate that expense is using specialized, high-performing architectures such as GPUs. Nevertheless, porting and optimizing a code for such a platform require a deep understanding of both the underlying hardware architecture and the algorithm at hand. Furthermore, for very large problems, multiple GPUs must work concurrently, which adds yet another layer of complexity to the codes. In this work, we have tackled the problem of porting and optimizing a 3D elastic wave propagation engine which supports both standard- and fully-staggered grids to multi-GPU clusters. At the single GPU level, we have proposed and evaluated many optimization strategies and adopted the best performing ones for our final code. At the distributed memory level, a domain decomposition approach has been used which allows for good scalability thanks to using asynchronous communications and I/O.

The Reconfigurable-Hardware Real-Time and Faster-Than-Real-Time Simulator for the Analysis of Electromagnetic Transients in Power Systems

The reconfigurable-hardware real-time power system simulator (RH-RTS) is a field-programmable gate-array (FPGA)-based real-time simulator that is developed based on the concept of simulators hardware reconfigurability (i.e., to change the underlying hardware architecture of the simulator to accommodate various power system topologies). The uniqueness of the RH-RTS is the underlying hardware architecture. The RH-RTS has a massively parallel customized hardware architecture that is tailored to the solution of the mathematical model of the power system under consideration. The RH-RTS enables the simulation of large power systems with a computation-time per simulation time-step in the range of tens of nanoseconds. Not only does the RH-RTS provide a means for real-time operation (e.g., for closed-loop testing of physical control/protection platforms in hardware-in-the-loop (HIL) configuration), it also provides a means for faster-than-real-time operation (e.g., for statistical switching studies). This paper provides validation and evaluation of the performance of the RH-RTS. This paper presents a case study involving the simulation of a power system in both real time and faster than real time. The computation time per simulation time-step is as low as 24 ns, for realistic size systems, which is, by far, the lowest computation time reported in the technical literature.