Underlying Data Flow Research Articles

Integrated Consideration of Data Flows and Life Cycle Assessment in Vehicle Dismantling processes

The pursuit of environmental sustainability and resource conservation has underscored the growing significance of the circular economy paradigm across industries. This transformation is particularly pertinent within the automotive industry, necessitating a profound restructuring of the value chain, with a specific focus on end-of-life considerations. Significant potential for circular economy arises from the thorough examination of end-of-life vehicles and processes, involving strategies such as component reuse, material recycling and primary resource reduction. Providing process-, product-, component-, and material-specific information at the end-of-life of automotive vehicles can improve decision-making regarding circular strategies. It also demands for new digital solutions. This paper addresses an integrated approach of data flow analysis and Life Cycle Assessment (LCA) to enable a comprehensive monitoring of the environmental impact of these processes. First, the use case of end-of-life dismantling processes is presented - including pyrotechnics neutralization, vehicle dehydration, disassembly of reuse components as well as vehicle compaction. Secondly, the data demand respective information and material flows is depicted. As a main result, the LCA data flow model specifically tailored to the end-of-life vehicle dismantling processes is described. This model serves as a fundamental basis for analyzing the environmental impact of end-of-life processes combined with the underlying data flow.

OPTIMAL FOLDING OF DATA FLOW GRAPHS BASED ON FINITE PROJECTIVE GEOMETRY USING VECTOR SPACE PARTITIONING

A number of computations exist, especially in area of error-control coding and matrix computations, whose underlying data flow graphs are based on finite projective-geometry (PG) based balanced bipartite graphs. Many of these applications of finite projective geometry are actively being researched upon, especially in coding theory. Almost all these applications need large bipartite graphs, whose nodes represent parallel computations. To reduce its implementation cost, reducing amount of system/hardware resources during design is an important engineering objective. In this context, we present a scheme to reduce resource utilization while designing systems modeled using PG-based graphs. In such systems, the number of processing units is equal to the number of vertices, each performing an atomic computation. We present a novel way of partitioning the vertex set assigned to various atomic computations, into blocks. Each block of partition is then assigned to a processing unit. A processing unit performs the computations corresponding to the vertices in the block assigned to it in a sequential fashion, thus creating the effect of folding the overall computation. The symmetric properties of projective space lattices enable us to develop a conflict-free communication schedule. We employed the technique of coset decomposition of a finite field for partitioning. The folding scheme achieves the best possible throughput, in lack of any overhead of shuffling data across memories while scheduling another computation on the same processing unit. We first provide a scheme for a finite projective space of dimension five, and the corresponding schedules. This specific scheme is then generalized for arbitrary finite projective spaces. Both the folding schemes have been verified by both simulation as well as hardware prototyping. For example, a semi-parallel decoder architecture for a new class of expander codes was designed and implemented using this scheme, with potential deployment in DVD-R/CD-ROM drives.

OPTIMAL FOLDING OF DATA FLOW GRAPHS BASED ON FINITE PROJECTIVE GEOMETRY USING VECTOR SPACE PARTITIONING

A number of computations exist, especially in area of error-control coding and matrix computations, whose underlying data flow graphs are based on finite projective-geometry (PG)-based balanced bipartite graphs. Many of these applications of finite projective geometry are actively being researched upon, especially in coding theory. Almost all these applications need large bipartite graphs, whose nodes represent parallel computations. To reduce its implementation cost, reducing amount of system/hardware resources during design is an important engineering objective. In this context, we present a scheme to reduce resource utilization while designing systems modeled using PG-based graphs. In such systems, the number of processing units is equal to the number of vertices, each performing an atomic computation. We present a novel way of partitioning the vertex set assigned to various atomic computations, into blocks. Each block of partition is then assigned to a processing unit. A processing unit performs the computations corresponding to the vertices in the block assigned to it in a sequential fashion, thus creating the effect of folding the overall computation. The symmetric properties of projective space lattices enable us to develop a conflict-free communication schedule. We employed the technique of coset decomposition of a finite field for partitioning. The folding scheme achieves the best possible throughput, in lack of any overhead of shuffling data across memories while scheduling another computation on the same processing unit. We first provide a scheme for a finite projective space of dimension five, and the corresponding schedules. This specific scheme is then generalized for arbitrary finite projective spaces. Both the folding schemes have been verified by both simulation as well as hardware prototyping. For example, a semi-parallel decoder architecture for a new class of expander codes was designed and implemented using this scheme, with potential deployment in DVD-R/CD-ROM drives.

An Efficient Algorithm for Delay Buffer Minimization

A data flow machine is said to be synchronized if for any vertex u in the underlying data flow graph, all inputs to vertex u arrive at the same time. An unsynchronized data flow machine with an acyclic underlying data flow graph can be transformed into a synchronized system by adding unit delay buffers to the system. This synchronization process can increase pipelining and throughout. Since the addition of delay buffers introduces hardware and area costs, it is desirable to insert the minimum number of delay buffers to synchronize a given data flow machine. Due to important applications in computer design, various delay buffer minimization problems have been studied by many researchers. Several optimal algorithms and heuristic algorithms have been proposed for slightly different models. In this paper, we introduce the concept of extensions of a directed acyclic graph to generalize and formalize several delay buffer minimization problems studied in the literature and present a polynomial time algorithm for computing the minimum delay buffer synchronization of a given data flow machine. Examples are provided to illustrate our algorithm and to show that our algorithm requires fewer delay buffers than previously published optimal algorithms for various models.

Buffer assignment algorithms on data driven ASICs

Data driven architectures have significant potential in the design of high performance ASICs. By exploiting the inherent parallelism in the application, these architectures can maximize pipelining. The key consideration involved with the design of a data driven ASIC is ensuring that throughput is maximized while a relatively low area is maintained. Optimal throughput can be realized by ensuring that all operands arrive simultaneously at their corresponding operator node. If this condition is achieved, the underlying data flow graph is said to be balanced. If the initial data flow graph is unbalanced, buffers must be inserted to prevent the clogging of the pipeline along the shorter paths. A novel algorithm for the assignment of buffers in a data flow graph is proposed. The method can also be applied to achieve wave-pipelining in digital systems under certain restrictions. The algorithm uses a new application of the retiming technique; the number of buffers here is shown to be equal to the minimum number of buffers achieved by integer programming techniques. We also discuss an extension of this algorithm which can further reduce the number of buffers by altering the DFG without affecting functionality or performance. The time complexities of the proposed algorithms are O(V/spl times/E) and O(V/sup 2//spl times/logV), respectively, a considerable improvement over the existing strategies. Also proposed is a novel buffer distribution algorithm that exploits a unique feature of data driven operation. This procedure maximizes throughput by inserting substantially fewer buffers than other techniques. Experimental results show that the proposed algorithms outperform the existing methods.

A computational model for static data flow machines

Computer architects have been constantly looking for new approaches to design high-performance machines. Data flow and VLSI offer two mutually supportive approaches towards a promising design for future super-computers. When very high speed computations are needed, data flow machines may be relied upon as an adequate solution in which extremely parallel processing is achieved. This paper presents a formal analysis for data flow machines. Moreover, the following three machines are considered: (1) MIT static data flow machine; (2) TI's DDP static data flow machine; (3) LAU data flow machine. These machines are investigated by making use of a reference model. The contributions of this paper include: (1) Developing a Data Flow Random Access Machine model (DFRAM), for first time, to serve as a formal modeling tool. Also, by making use of this model one can calculate the time cost of various static data machines, as well as the performance of these machines. (2) Constructing a practical Data Flow Simulator (DFS) on the basis of the DFRAM model. Such DFS is modular and portable and can be implemented with less sophistication. The DFS is used not only to study the performance of the underlying data flow machines but also to verify the DFRAM model.