Epoxy Underfill Research Articles

Design and Architecture Definition for Advanced 3D Fan-Out Wafer-Level Packaging

Advanced 2.5D/3D wafer-level fan-out packaging technologies have been studied widely in literature and industry in recent years. Miniaturization, reduction in manufacturing costs, improvement in performance, and lower power consumption using packaging technologies drive increase in interconnect density and pitch scaling. Heterogeneous systems in package used in advanced packaging often include a combination of silicon, epoxy underfill or mold compounds, and organic or inorganic passivation or redistribution layers. This heterogeneity poses challenges with manufacturability, process selection, package architecture, and test vehicle design. The coefficient of thermal expansion mismatch, wafer warpage, and wafer yield are some of the critical process challenges. Delamination of silicon side wall or passivation to epoxy underfill or mold compound, joint fatigue are critical reliability challenges. This article explores various processes and reliability challenges with 3D wafer-level fan-out packaging and provides package design and architecture guidelines to overcome these failure modes. Stacked die-to-wafer test vehicles have been used for data collection. Different assembly materials, processes, and tooling have been evaluated to define comprehensive design rules.

Underfill epoxy has high glass-transition temperature and low viscosity

Underfill epoxy has high glass-transition temperature and low viscosity

Wafer-Scale Hybrid Integration of InP DFB Lasers on Si Photonics by Flip-Chip Bonding with sub-300nm Alignment Precision

InP DFB lasers are flip-chip bonded to 300mm Si photonic wafers using a pick-and-place tool with an advanced vision system, realizing high-precision and high-throughput passive assembly. By careful co-design of the InP-Si Photonics electrical, optical and mechanical interface, as well as dedicated alignment fiducials, sub-300nm post-bonding alignment precision is realized in a 25s cycle time. Optical coupling losses of -1.5±-0.5dB are achieved at 1550nm wavelength after epoxy underfill, with up to 40 mW of optical power coupled to the SiN waveguides on the Si photonics wafer. The bonding interface adds less than 10% to the series resistance of the laser diodes and post-bonding thermal resistance is measured to be 76K/W (or 27K.mm/W), mostly dominated by heat spreading resistance in the InP lasers as suggested by in-depth thermal modeling. Although the assembled lasers suffer from significant, unintentional optical backreflection from the fiber grating couplers used for optical characterization, laser linewidths well below 1MHz have been measured under specific drive conditions, as supported by a detailed laser noise analysis. Finally, we demonstrate the ability of bonded laser assemblies to pass early reliability tests.

Experiments and modelling of adhesive failure initiation of an epoxy underfill: a study of electronic packaging survivability

Experiments and modelling of adhesive failure initiation of an epoxy underfill: a study of electronic packaging survivability

Experiments and modelling of adhesive failure initiation of an epoxy underfill: a study of electronic packaging survivability

Experiments and modelling of adhesive failure initiation of an epoxy underfill: a study of electronic packaging survivability

Formation of Ohmic Contacts to n-GaAs at Temperatures Compatible with Indium Flip-Chip Bonding

Heterogenous integration of III-V photodetectors with Si readout circuitry is an enabling technology for applications including focal plane arrays [1] and concentrating solar cells [2, 3]. Typical integration schemes include low temperature flip-chip bonding using indium (In) bump bonds, followed by epoxy underfill, and mechanical and/or chemical removal of the III-V substrate to expose the epitaxially grown detector layers [1]. For maximum flexibility in device design and processing, it is desirable to be able to form low resistance illumination-side contacts to either p-type or n-type layers after flip-chip bonding. Formation of non-alloyed contacts to p-GaAs is relatively straightforward and can be readily implemented after flip-chip bonding [4]. Conventional contacts to n-GaAs are formed by evaporation of Ge/Au/Ni followed by a rapid thermal annealing step at 400 °C [4], considerably above the 156 °C melting point of In and above the degradation temperature of many standard underfill epoxies. Several groups have studied the formation of ohmic contacts to n-GaAs through low temperature annealing of Pd/Ge/Au metal stacks [3, 5, 6], however all reports to date have used annealing temperatures near or above the melting point of In. In this work, we report the formation of ohmic contacts with a specific contact resistivity as low as 5.6×10-6 Ω-cm2 after annealing at a temperature of 140 °C, significantly below the In melting point. Figures 1 and 2 show experimental results of transfer line method (TLM) test structures measured on an epitaxially grown 800 nm thick, 1x1018 cm-3 n-GaAs layer with 7 nm Pd/ 50 nm Ge/ 200 nm Au contacts patterned with photolithography and evaporation. The samples were annealed in an oven with a N2 ambient and measured repeatedly throughout the annealing process. We observe a transition from Schottky to ohmic behavior after 10 hours of annealing followed by a steady decrease in resistance for annealing times out to 48 hours. A companion sample that had been flip-chip bonded with In bumps and underfilled with Epotek 301 epoxy showed no degradation after annealing. The black line in Fig. 1 is provided as a reference of the measured specific contact resistivity of a standard Ge/Au/Ni/Au metal stack deposited on the same n-GaAs layer after a 30 second, 400 °C anneal. The creation of low-resistance ohmic contacts to n-GaAs at this low temperature is an enabling technology for III-V heterogeneous integration efforts with a wide array of temperature-sensitive materials such as In, epoxies, photoresists, and plastics. Acknowledgment Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government.

(Invited) Heterogeneous Integration of III-V Semiconductors for Imaging and High-Speed Communication

Heterogenous integration of III-V compound semiconductors with Si circuitry is an enabling technology for applications including high-bandwidth communications [1], focal plane arrays [2] and concentrating solar cells [3, 4]. Typical integration schemes include low temperature flip-chip bonding using indium bump bonds along with epoxy underfill and may include the integration of micro-optics for collimation and focusing. In this talk, I will discuss previous and ongoing compound semiconductor heterogenous integration efforts at Sandia National Laboratories and the challenges involved in forming high-yield devices. Specific programs to be discussed include the ARPA-E MOSAIC solar concentrator (Fig. 1), infrared focal plan arrays (Fig. 2), and the recently-awarded DARPA PIPES ultra-low-energy-per-bit photonic transceiver. References Ciftcioglu, et al, “3-D integrated heterogenous intra-chip free-space optical interconnect,” Opt. Express, vol. 20 2012.W. Peters, et al., “Resonant ultrathin infrared detectors enabling high quantum efficiency,” IEEE RAPID, 2018.Li, et al., “Wafer integrated micro-scale concentrating photovoltaics,” Prog. Photovoltaics, vol. 26, 2018.H. Jared, et al., “Integration of wafer-level solar cells and micro-optic concentrators for micro-scale concentrating photovoltaics,” ASPE Annual Meeting, 2017. Acknowledgment This work was supported in part by the Laboratory Directed Research and Development program at Sandia National Laboratories. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government. Figure 1

Removing epoxy underfill between neighbouring components using acid for component chip-off

In addition to traditional high temperature eutectic soldering, the use of underfill epoxy to glue the electronic components to the PCB (memory, CPU, cryptographic chips) has now become the norm among mobile phone manufacturers, e.g. Apple, BlackBerry and Samsung. Currently, this technique is the best solution to protect components against various mechanical stresses and improve reliability. Unfortunately, traditional techniques (chip-off or lapping) have become impossible to apply to underfilled components without destroying them or without moving peripheral electronic components. These component movements make the board unusable or require many hours of expensive repairs and specific hardware.Acids and their use can be of interest in the digital forensics domain. Firstly, they can be used to de-capsulate the packaging of the electronic components before reading the chip (physical dump by chip-on), or to carry out reverse engineering of secure systems by micro-reading techniques of the silicon chip. Moreover, as we show in this paper, with the arrival of the latest generations of mobile phones, acid mixtures can be of interest if investigators want to use classical chip-off method (or the legal transplantation of damaged phones) for phones using underfill epoxy which cover the neighbouring components together (CPU, memory, capacitors, etc.).This work introduces a new method called “underfill acid corrosion”. The proposed process is based on the use of different mixtures of acids heated to various temperatures. We quantitatively study the influencing factors on the efficiency of acid corrosions on industrial underfill and present our results. Finally, we present our optimised process to unsolder electronic components which are glued together by an industrial high temperature underfill epoxy, without destroying the targeted electronic components and mobile phones PCB.

Predicting delamination in multilayer composite circuit boards with bonded microelectronic components

The present work developed a mixed-mode cohesive zone model (CZM) with a mode I failure criterion to predict the delamination bending loads of multilayer, composite printed circuit boards (PCBs) assembled with soldered ball grid array (BGA) components that were reinforced with an underfill epoxy adhesive. Two different delamination modes were observed in these microelectronic assemblies: delamination at the interface between the solder mask and the first conducting layer of the PCB, and PCB subsurface delamination at the interface between the epoxy and glass fibers of one of the prepreg layers. The cohesive parameters for each of the two crack paths were obtained from fracture tests of bending test specimens consisting of PCB substrates bonded with the underfill adhesive. The model provided relatively accurate predictions of the crack paths and the bending strength of the actual underfilled BGA-PCB assemblies for a range of adhesive fillet sizes, PCB stiffnesses, and strain rates.

High-Temperature Interfacial Adhesion Strength Measurement in Electronic Packaging Using the Double Cantilever Beam Method

This paper describes the use of the double cantilever beam (DCB) method for characterizing the adhesion strength of interfaces in advanced microelectronic packages at room and high temperatures. Those interfaces include silicon–epoxy underfill, solder resist–epoxy underfill and epoxy mold compounds (EMCs), and die passivation materials–epoxy underfill materials. A unique sample preparation technique was developed for DCB testing of each interface in order to avoid the testing challenges specific to that interface—for example, silicon cracking and voiding in silicon–underfill samples and cracking of solder resist films in solder resist–underfill samples. An asymmetric DCB configuration (i.e., different cantilever beam thickness on top compared to the bottom) was found to be more effective in maintaining the crack at the interface of interest and in reducing the occurrence of cohesive cracking when compared to symmetric DCB samples. Furthermore, in order to characterize the adhesion strength of those interfaces at elevated temperatures seen during package assembly and end-user testing, an environmental chamber was designed and fabricated to rapidly and uniformly heat the DCB samples for testing at high temperatures. This chamber was used to successfully measure the adhesion strength of silicon–epoxy underfill samples at temperatures up to 260 °C, which is the typical maximum temperature experienced by electronic packages during solder reflow. For the epoxy underfills tested in this study, the DCB samples failed cohesively within the underfill at room temperature but started failing adhesively at temperatures near 150 °C. Adhesion strength measurements also showed a clear degradation with temperature. Several other case studies using DCB for material selection and assembly process optimization are also discussed. Finally, fractography results of the fractured surfaces are presented for better understanding of the failure mode.

Thermal and Viscoelastic Properties of Underfill Using hexagonal Boron Nitride (hBN) Nanofiller

Abstract Epon 826 epoxy resin in conjunction with Epikure 3140 curing agent was used in this study to fabricate underfill composites. Nanofiller of 500nm hexagonal boron nitride (hBN) was incorporated in the underfill epoxy using ultrasonication technique to alter their thermal and viscoelastic properties. Filler contents ranging from 1% to 5% volume fraction (vol.%) were used to investigate changes in thermal behavior and viscoelasticity of underfill with an increase in filler loading. Thermal analysis has shown an increase in thermal conductivity of the underfill by increasing the filler loading. Using 5% vol.% of 500nm hBN nanofiller a thermal conductivity of 0.32 W/m.K was obtained as compared to neat epoxy with thermal conductivity of about 0.2 W/m.K, showing an enhancement in thermal conductivity of the underfill material. Furthermore, studying viscoelastic properties of fabricated underfills suggested the influence of filler and filler loading on viscoelasticity of underfill.

Precise underfill dispense in high-throughput chip-on-wafer packaging

In today's microelectronic packaging, components are continuously designed smaller and assembled more densely to allow more functions to fit into compact portable devices. To enable this trend, more manufacturers are using flip chips that have more I/O's and smaller bumps sizes. This has introduced underfill dispensing that fills the gap between the flip chip and the substrate with polymer epoxy to help reduce thermal and mechanical stress at the bonding interface. In device packaging, the demands for cost reduction and miniaturization encourage the use of wafer-level packaging, such as the chip-on-wafer process. As a result, the challenges to this process have grown exponentially, and so have the challenges to underfill dispensing. For example, to package a device with a chip-last process, the keep-out-zone (KOZ) for underfill epoxy placement to nearby components is shrinking, e.g. from 700um to 300–500um within one year. A high-precision, high-throughput underfill dispensing process has been developed to conquer these challenges. This underfill process is being used in production for chip-on-wafer packaging. In one example, underfill must be dispensed within KOZ 300–500um at UPH 4000. New equipment and new dispensing techniques are under development to further push the limit on higher throughput and precision. Key words: underfill, dispense, microelectronic packaging, device packaging, wafer-level packaging, chip-on-wafer, chip-last, keep-out-zone, precision, throughput

Effect of adhesive fillet geometry on bond strength between microelectronic components and composite circuit boards

Printed circuit boards (PCBs) assembled with ball grid array (BGA) microelectronics packages were tested in a double cantilever beam (DCB) configuration. The results were compared for a filled and an unfilled underfill epoxy adhesive as well as a cyanoacrylate adhesive. The original fillet, formed in the underfilling process, was modified to create fillets of different sizes. Regardless of the underfill thermal and mechanical properties as well as its curing profile, the crack initiation load and the failure mode were solely a function of the size of the underfill fillet, and the failure always initiated within the PCB. Moreover, the strength of the underfilled solder joints was increased significantly (approximately 100%) by the presence of a relatively large fillet. This effect of the underfill fillet on the crack path and the fracture load was then examined in terms of differences in the stress states using a finite element model.

Characterization of polymer/epoxy buried interfaces with silane adhesion promoters before and after hygrothermal aging for the elucidation of molecular level details relevant to adhesion

Buried interfacial structures containing epoxy underfills are incredibly important in the microelectronics industry and their structures determine the interfacial adhesion properties and ultimately their lifetime.

Wafer-level capping and sealing of heat sensitive substances and liquids with gold gaskets

This paper reports on a novel wafer-level packaging method employing gold gaskets and an epoxy underfill. The packaging is done at room-temperature and atmospheric pressure. The mild packaging conditions allow the encapsulation of sensitive devices. The method is demonstrated for two applications; the wafer-level encapsulation of a liquid and the wafer-level packaging of a photonic gas sensor containing heat sensitive dye-films.

Molecular Level Understanding of Adhesion Mechanisms at the Epoxy/Polymer Interfaces

It is important to understand the buried interfacial structures containing epoxy underfills as such structures determine the interfacial adhesion properties. Weak adhesion or delamination at such interfaces leads to failure of microelectronic devices. Sum frequency generation (SFG) vibrational spectroscopy was used to examine buried interfaces at polymer/model epoxy and polymer/commercial epoxy resins (used as underfills in flip chip devices) at the molecular level. We investigated a model epoxy: bisphenol A digylcidyl ether (BADGE) at the interfaces of poly (ethylene terephthalate) (PET) before and after curing. Furthermore, small amounts of different silanes including (3-glycidoxypropyl) trimethoxysilane (γ-GPS), (3-Aminopropyl)trimethoxysilane (ATMS), Octadecyltrimethoxysilane (OTMS(18C)), and Octyltrimethoxysilane (OTMS(8C)) were mixed with BADGE. Silane influences on the polymer/epoxy interfacial structures were studied. SFG was also used to study molecular interfacial structures between polymers and two commercial epoxy resins. The interfacial structures probed by SFG were correlated to the adhesion strengths measured for corresponding interfaces. The results indicated that a small amount of silane molecules added to epoxy could substantially change the polymer/epoxy interfacial structure, greatly affecting the adhesion strength at the interface. It was found that ordered methyl groups at the interface lead to weak adhesion, and disordered interfaces lead to strong adhesion.

Surface and Buried Interfacial Structures of Epoxy Resins Used as Underfills Studied by Sum Frequency Generation Vibrational Spectroscopy

Flip chip technology has greatly improved the performance of semiconductor devices, but relies heavily on the performance of epoxy underfill adhesives. Because epoxy underfills are cured in situ in flip chip semiconductor devices, understanding their surface and interfacial structures is critical for understanding their adhesion to various substrates. Here, sum frequency generation (SFG) vibrational spectroscopy was used to study surface and buried interfacial structures of two model epoxy resins used as underfills in flip chip devices, bisphenol A digylcidyl ether (BADGE) and 1,4-butanediol diglycidyl ether (BDDGE). The surface structures of these epoxies were compared before and after cure, and the orientations of their surface functional groups were deduced to understand how surface structural changes during cure may affect adhesion properties. Further, the effect of moisture exposure, a known cause of adhesion failure, on surface structures was studied. It was found that the BADGE surface significantly restructured upon moisture exposure while the BDDGE surface did not, showing that BADGE adhesives may be more prone to moisture-induced delamination. Lastly, although surface structure can give some insight into adhesion, buried interfacial structures more directly correspond to adhesion properties of polymers. SFG was used to study buried interfaces between deuterated polystyrene (d-PS) and the epoxies before and after moisture exposure. It was shown that moisture exposure acted to disorder the buried interfaces, most likely due to swelling. These results correlated with lap shear adhesion testing showing a decrease in adhesion strength after moisture exposure. The presented work showed that surface and interfacial structures can be correlated to adhesive strength and may be helpful in understanding and designing optimized epoxy underfill adhesives.

Estimation of Curing Profile's Parameters for Flip Chip Packaging Using DSC and TGA

This paper presents the method to estimate curing profile's parameters for curing process of Moisture Resistance Cyanate Ester (MRCE) based underfill used in Flip Chip Ceramic Ball Grid Array (FC-CBGA). The two steps curing profile was found to eliminate voids formation in underfill during curing process. The important parameters in two steps curing profile such as first fixed temperature and duration of second temperature rise were estimated by superimposed of cure initiation curve and weight percentage loss curve of underfill epoxy material. Differential Scanning Calorimeter (DSC) analysis was carried out to characterize the cure kinetics reaction of underfill epoxy and produced the cure initiation curve. Thermal Gravimetric Analysis (TGA) was performed to characterize the weight loss of underfill and produced the weight loss curve. It was estimated that the first fixed temperature and duration of second temperature rise for two steps curing profile were 100 oC and 60-80 minutes respectively. The simulation experiment was conducted to verify the profile and no voids formation observed along this curing process.

The Study of Underfill Epoxy Hardness in Reducing Curing Process Time for Flip Chip Packaging

Underfilling is the vital process to reduce the impact of the thermal stress that results from the mismatch in the co-efficient of thermal expansion (CTE) between the silicon chip and the substrate in Flip Chip Packaging. This paper reported the pattern of underfill’s hardness during curing process for large die Ceramic Flip Chip Ball Grid Array (FC-CBGA). A commercial amine based underfill epoxy was dispensed into HiCTE FC-CBGA and cured in curing oven under a new method of two-step curing profile. Nano-identation test was employed to investigate the hardness of underfill epoxy during curing steps. The result has shown the almost similar hardness of fillet area and centre of the package after cured which presented uniformity of curing states. The total curing time/cycle in production was potentially reduced due to no significant different of hardness after 60 min and 120 min during the period of second hold temperature.

An Optimization of Two-Steps Curing Profile to Eliminate Voids Formation in Underfill Epoxy for Hi-CTE Flip Chip Packaging

Underfilling is the preferred process to reduce the impact of the thermal stress that results from the mismatch in the coefficient of thermal expansion (CTE) between the silicon chip and the substrate in Flip Chip Packaging. Voids formation in underfill is considered as failure in flip chip manufacturing process. Voids formation possibly caused by several factors such as poor soldering and flux residue during die attach process, voids entrapment due moisture contamination, dispense pattern process and setting up the curing process. This paper presents the optimization of two steps curing profile in order to reduce voids formation in underfill for Hi-CTE Flip Chip Ceramic Ball Grid Array Package (FC-CBGA). A C-Mode Scanning Aqoustic Microscopy (C-SAM) was used to scan the total count of voids after curing process. Statistic analysis was conducted to analyze the suitable curing profile in order to minimize or eliminate the voids formation. It was shown that the two steps curing profile provided solution for void elimination.