UML State Machine Diagrams Research Articles

AGL: Incorporating behavioral aspects into domain-driven design

Domain-driven design (DDD) aims to iteratively develop software around a realistic domain model. Recent research in DDD has been focusing on using annotation-based domain-specific languages (aDSLs) to build the domain model. However, within current approaches behavioral aspects, that are often represented using UML Activity and State machine diagrams, are not explicitly captured in the domain model. The focus of this paper is to introduce a new approach for incorporating behavioral aspects into domain models within the Domain-Driven Design (DDD) approach. The proposed approach involves using a new activity graph language (AGL) as an aDSL for representing behavioral aspects within a unified domain model. This integration of AGL and the previously developed aDSL (DCSLto represent domain models) aims to achieve three important features of DDD: feasibility, productivity, and understandability. Our approach involves building a unified class model in DCSLwithin a domain-driven architecture, which uses the annotation attachment feature of the host programming language (such as Java) to attach AGL activity graphs directly to the activity class of the unified class model, resulting in a unified domain model. In this work, we define the abstract and concrete syntax of AGL. To demonstrate our method, we use a Java framework called jDomainApp and evaluate AGL through a case study to show that it is expressive and practical for real-world software. This paper presents two contributions. Firstly, it proposes a mechanism to include behavioral aspects in a unified domain model by introducing a new aDSL called AGL to represent domain behaviors. Secondly, it presents a unified modeling method for domain-driven software development. Our method significantly extends the state-of-the-art in DDD in two important fronts: constructing a unified domain model for both structural and behavioral aspects of domain models and bridging the gaps between model and code.

Formal Verification of Control Modules in Cyber-Physical Systems.

The paper proposes a novel formal verification method for a state-based control module of a cyber-physical system. The initial specification in the form of user-friendly UML state machine diagrams is written as an abstract rule-based logical model. The logical model is then used both for formal verification using the model checking technique and for prototype implementation in FPGA devices. The model is automatically transformed into a verifiable model in nuXmv format and into synthesizable code in VHDL language, which ensures that the resulting models are consistent with each other. It also allows the early detection of any errors related to the specification. A case study of a manufacturing automation system is presented to illustrate the approach.

Regression testing of object-oriented systems using UML state machine diagram and sequence diagram

The software requirements are modelled using UML state machine diagram and UML sequence diagram. The different features of both the diagrams are combined and an intermediate graph, i.e., state sequence graph (SSG) is generated. The affected nodes, due to different changes in the past versions of the applications are stored for further analysis. Whenever, a new version of the software is developed, and it is under regression testing, test scenario prioritisation is carried out by finding the frequent pattern from the stored modification history. Different other factors like number of message passing, number of state changes etc. also contribute in prioritising the test cases. The proposed approach is applied on different case studies and the results are recorded. This approach is found to be very efficient when evaluated using prioritisation metric and compared with other related work.

Regression testing of object-oriented systems using UML state machine diagram and sequence diagram

The software requirements are modelled using UML state machine diagram and UML sequence diagram. The different features of both the diagrams are combined and an intermediate graph, i.e., state sequence graph (SSG) is generated. The affected nodes, due to different changes in the past versions of the applications are stored for further analysis. Whenever, a new version of the software is developed, and it is under regression testing, test scenario prioritisation is carried out by finding the frequent pattern from the stored modification history. Different other factors like number of message passing, number of state changes etc. also contribute in prioritising the test cases. The proposed approach is applied on different case studies and the results are recorded. This approach is found to be very efficient when evaluated using prioritisation metric and compared with other related work.

Test scenario prioritization for object-oriented systems using UML diagram

The exponential growth in the complexity of product requirements has raised the importance of software testing. Software change management is one of the major challenge and regression testing provides a solution in this regard. Regresion testing is performed to find out the effect of the modified component on the other components present in the application. Here, a behavioural model i.e. an UML State Machine Diagram (SMD) is used to model the system requirements. Further, an intermediate State Machine Graph (SMG) is constructed from SMD. The test scenarios are generated by identifying the paths those are linearly independent of each other. These test scenarios are validated for code coverage using dynamic program analysis technique. Then, by traversing the SMG, nodes are identified those got affected due to the different change carried away in the software. A repository is maintained to store the information about affected nodes periodically. Next time, during regression testing, pattern of nodes those are frequently affected, are identified from the stored data and these patterns helps in test case prioritization. Two more criterias i.e. functional priority set by the client and number of times the user accessed the user interface are also added up. Further, it calculates the total priority value of a test scenarios and test-scenarios are arranged in depending upon their total priority value. Moelling dynamic nature of the application as well as applying mining on the historical data makes the proposed approach more efficient when compared with the related works.

Firefly optimization technique based test scenario generation and prioritization

Model-based testing shows a significant role-play in the area of software testing. This paper presents a new automatic test scenarios generation technique using UML state machine diagram having composite states. The intention of this research is to generate test scenarios for concurrent and composite states in state machines using the proposed algorithm SMToTSG (State Machine To Test Scenarios Generation). We have prioritized the test scenarios using Firefly optimization algorithm. We have used state-based coverage criteria such as state, transition, transition pair coverage to evaluate the efficiency of the proposed algorithm. The proposed approach is useful for feasible test scenario generation. Generating exhaustive test scenarios for all concurrent interdependent sequences is very difficult. In this paper, we generate the important test scenarios in the presence of concurrency in composite models. After prioritization, we apply Average Percentage Fault Detection (APFD) metric to calculate the efficiency of the prioritized test scenarios.

Verification of Model Transformations Using Isabelle/HOL and Scala

Model transformations have proved to be powerful in the development of critical systems. According to their intents, they have been used in many domains such as models refinement, simulation, and domain semantics. The formal methods have been successful in the verification and validation of critical systems, and in particular, in the formalization of UML, BPMN, and AADL. However, little research has been done on verifying the transformation itself. In this paper, we extend our previous work using Isabelle/HOL that transforms UML State Machine Diagrams (SMD) to Colored Petri nets (CPN) models and proves that certain structural properties of this transformation are correct. For example, the structural property: “for each final state of a SMD model a corresponding place in CPN model should be generated by the transformation” is described and checked using Isabelle/HOL as invariant property. In the current work, we use Scala as environment of executing Isabelle/HOL specifications and we perform the verified transformation using Scala. Moreover, we demonstrate our approach using another case study of transforming BPMN (Business Process Model and Notation) models into Petri nets models and verify the correctness of certain structural properties of this transformation.

Risk based Test Case Prioritization using UML State Machine Diagram

Risk based Test Case Prioritization using UML State Machine Diagram

Software Performance Evaluation Utilizing UML Specification and SRN Model and Their Formal Representation

A distributed system is a complex system. Developing complex systems is a demanding task when attempting to achieve functional and non-functional properties such as synchronization, communication, fault tolerance. These properties impose immense complexities on the design, development, and implementation of a distributed system that incur massive effort and cost a large amount of money. Therefore, it is vital to ensure that the system must satisfy the functional and non-functional properties once the system development process is finished. Once a distributed system is developed, it is very difficult, time consuming, and expensive to conduct any modification in its architecture. As a result, the quantitative analysis of a complex distributed system at the early stage of the development process is always an essential and intricate endeavor. To meet the challenge of conducting quantitative analysis at the early stage of the system development process, this thesis introduces an extensive framework for performance and performability evaluation of a distributed system. The goal of the performance modeling framework is the assessment of the non-functional properties of the distributed system at an early stage based on the system’s functional description and deployment mapping of service components over an execution environment. The performability framework is the extension of the performance modeling framework. The extended part of the performability modeling framework considers the behavioral change of the system components due to failures. This later reveals how such behavioral changes affect the system performance. The reusable specification of service components is the main specification unit of our framework. The specification of the reusable service component is realized through UML collaboration and activity. Activity diagrams are used to aid the illustration of the complete behavior of a system, which includes both local behavior of the service components and the necessary interactions among them. Reusable building blocks are collaborative in nature, which allows them to span across several participating components. The local behavior and interaction among the participating components are realized in an encapsulated way, which can be further reused to develop new applications. The assignment of service components that capture the system functional behavior of the physical components is recognized as deployment mapping. Deployment mapping has a significant impact on ensuring the non-functional properties provided by the system in a resource limited environment. This thesis also specifies the deployment mapping of service components using UML deployment diagrams. The focus of the deployment mapping is on considering the non-functional requirements such that the performance of a service or a system on a particular physical infrastructure can be assessed in a fully distributed manner and for large scale. In addition, a UML state machine diagram is utilized in our performability modeling framework to capture the dependability behavior of the system components. To conduct the performance and performability evaluation of a distributed system, the UML model is transformed into analytic models that provide performance and performability evaluation results. The significance of using an analytical model is because of its well-established mathematical formula and the availability of model evaluation tools. We have specified an automated transformation process that is performed in an efficient and scalable way through the use of model transformation rules to achieve model transformation. To analyze the correctness of the model transformation process, we have used temporal logic, specifically cTLA, to formalize the UML specification style. This, in turn, provides the opportunity for model validation. The motivation of applying cTLA is to take advantage of its well-established method to illustrate various forms of structures and actions by exploiting a variety of operators and techniques, which is wonderfully compatible with UML collaborations, activities, deployment, and state machine diagram. The framework is applied to artificial and real case studies to generate performance and performability results at the early stage of the system development process. The modeling process is supported by a set of tools, including Arctis and SHARPE with the incremental model checking facility. Arctis is used for specifying the system functional behavior. The evaluation of the performance and performability models generated by the framework is achieved using SHARPE.

Representing Security Specifications in UML State Machine Diagrams

Abstract Security specifications are controls and constraints on the behavior of the software and can be used to develop more secure software from the beginning. Many specification languages have been proposed to represent security specifications. However, all these specification languages are at a higher level of abstraction and can only be used to represent overall business-level design decisions. Such specifications provide guidance to the developers but do not lay out the details of the dynamic behavior that has to be implemented during the coding phase. In this paper, we propose to use UML state machine diagrams to represent detailed dynamic behavior of design-level security specifications. We argue that these behaviors when used by the developer for implementation will enable them to avoid crucial security vulnerabilities.

From UML Specification into FPGA Implementation

In the paper a method of using the Unified Modeling Language for specification of digital systems, especially logic controllers, is presented. The proposed method is based mainly on the UML state machine diagrams and uses Hierarchical Concurrent Finite State Machines (HCFSMs) as a temporary model. The paper shows a way to transform the UML diagrams, expressed in XML language, to the form that is acceptable by reconfigurable FPGAs (Field Programmable Gate Arrays). The UML specification is used to generate an effective program in Hardware Description Languages (HDLs), especially Verilog.

An Object-Oriented Approach To Generate Java Code From Hierarchical-Concurrent and History States

UML is widely accepted and practiced in industries for modeling and design of software systems. Software requirements and design are very important parts of software development. UML State Machine diagram is an important formalism to model the dynamic behavior of the system. In this paper, we present a new approach to generate compact and efficient Java code from complex state machine involving hierarchical-concurrent states; the proposed code can be used as a Java implementation pattern for automatic code generation for an object-oriented system. The main idea of our study is using Java Enum type with attributes for implementing complex state machines.

Estimation of Energy Consumption for Mobile Software using UML State Machine Diagram

The application software operated on mobile device like a smart phone is hard to ensure continuously provision of stable services because of limited resource like a battery. Therefore the requirements on the energy consumption of mobile software become one of critical issues in the software development. To cover the problem that the energy consumption requirement of software was not satisfied when code development is completed, we propose an energy consumption analysis technique using software design model, UML state machine diagram. The design model is transferred to Coloured Petri-Net to estimate the energy consumption. Our technique gives a chance to reduce the energy consumption in the process of software development

From UML State Machine Diagram into FPGA Implementation

In the paper a method of using the Unified Modeling Language diagrams for specification of digital systems, especially logic controllers, is presented. The proposed method is based mainly on the UML state machine diagrams and uses Hierarchical Concurrent Finite State Machines (HCFSMs) as a temporary model. The paper shows a way to transform the UML diagrams to the form that is acceptable by reconfigurable FPGAs (Field Programmable Gate Arrays). The UML specification is used to generate an effective program in Hardware Description Languages (HDLs), especially Verilog.

Partial Reconfiguration in the Field of Logic Controllers Design

The paper presents method for logic controllers multi context implementation by means of partial reconfiguration. The UML state machine diagram specifies the behaviour of the logic controller. Multi context functionality is specified at the specification level as variants of the composite state. Each composite state, both orthogonal or compositional, describes specific functional requirement of the control process. The functional decomposition provided by composite states is required by the dynamic partial reconfiguration flow. The state machines specified by UML state machine diagrams are transformed into hierarchical configurable Petri nets (HCfgPN). HCfgPN are a Petri nets variant with the direct support of the exceptions handling mechanism. The paper presents placesoriented method for HCfgPN description in Verilog language. In the paper proposed methodology was illustrated by means of simple industrial control process.

Towards a Formal Semantics for UML/MARTE State Machines Based on Hierarchical Timed Automata

UML is a widely-used, general purpose modeling language. But its lack of a rigorous semantics forbids the thorough analysis of designed solution, and thus precludes the discovery of significant problems at design time. To bridge the gap, the paper investigates the underlying semantics of UML state machine diagrams, along with the time-related modeling elements of MARTE, the profile for modeling and analysis of real-time embedded systems, and proposes a formal operational semantics based on extended hierarchical timed automata. The approach is exemplified on a simple example taken from the automotive domain. Verification is accomplished by translating designed models into the input language of the UPPAAL model checker.

Hierarchical Configurable Petri Net Modeling in VHDL

Abstract The paper presents method for hierarchical configurable Petri nets description in VHDL language. Dual model is an alternative way for behavioral description of the discrete control process. Dual model consists of two correlated models: UML state machine diagram and hierarchical configurable Petri net (HCfgPN). HCfgPN are Petri nets variant with direct support of exceptions handling mechanism. Logical synthesis of dual model is realized by the description of HCfgPN model by means of hardware description language. The paper presents placesoriented method for HCfgPN description in VHDL language

UML 상태 기계를 이용한 임베디드 소프트웨어의 소모 전력 분석

A wide variety of smartphone applications is increasing the usage time of smartphone. Due to the increased time, it becomes difficult to providing stable services to users with limited battery capacity. The past works have been performed the power management of mobile device toward long-lasting battery development or low-power electric devices. However as the complexity of software embedded into system are increased, the research interests of the software power analysis is also increased. Among these studies on the software power analysis, model-based analysis technique is one of major interests because it can be able to analyze the power consumption before the development of source codes, then the analysis result can be used in the development of the software system, This paper suggests a model-based power analysis technique using UML state machine diagram. Our proposed technique estimates the power consumption by the simulation of Perti-net which is transformed from the state machine diagram.

Petri Net Based Specification in the Design of Logic Controllers with Exception Handling Mechanism

Petri Net Based Specification in the Design of Logic Controllers with Exception Handling Mechanism Hierarchical Petri nets beside UML state machine diagrams, sequentional function charts (SFC) and hierarchical concurrent state machines are common solution for specification of logic controllers. These specification formats provide both concurrency and modeling on multi levels of abstraction (hierarchic approach). But only state machine diagrams supports exceptions handling in direct way. Program model presented in form of state machine diagram may be later transformed into a program in the SFC language or transformed in the Petri Net and implemented in the FPGA structure. Similarity between SFC language and Petri Nets give us lot of tools for analysis such control system. Article presents new approach for exceptions handling in hierarchical Petri nets as formal specification for logic controllers. Proposed method of specification can be used independently or as a part of dual specification (correlated state machine diagram and hierarchical configurable Petri Net).

Model Checking Consistency of UML Diagrams Using Alloy

In this paper, we proposed a method for detecting consistency violation between UML state machine diagrams and communication diagrams using Alloy. Using input language of Alloy, the proposed method expresses system behaviors described by state machine diagrams, message sequences described by communication diagrams, and a consistency property. As a result of application for an example system, we confirmed that consistency violation could be detected using Alloy correctly. Keywords—model checking, UML, state machine diagrams, communicatiuon diagram, Alloy.