Ultrathin High-k Gate Dielectrics Research Articles

Epitaxial Ge on Standard STI Patterned Si Wafers: High Quality Virtual Substrates for Ge pMOS and III/V nMOS

Further improving CMOS performance beyond the 22 nm generation likely requires the use of high mobility channel materials. Complementary integration of different materials on Si can be realized with selective epitaxial growth. We present two fabrication schemes for Ge virtual substrates on standard Si STI wafers. This reduces the fabrication cost of these virtual substrates as it omits the complicated isolation scheme in blanket Ge. The low topography enables integration of ultra thin high-K gate dielectrics. The fabrication schemes are compatible with uni-axial stress techniques. Both modules include an anneal at 850 {degree sign}C to reduce the threading dislocation density down to 4x108 cm-2 and 1x107 cm-2, respectively. We are able to fabricate high quality Ge virtual substrates for pMOS devices as well as suitable starting surfaces for selective epitaxial III/V growth. The latter one will be illustrated by preliminary results of selective epitaxial InGaAs growth on virtual Ge substrates.

Effective Capture Cross-Sections of Traps in High-k Gate Dielectrics

We report an experimental study of captures cross-sections of traps in some ultra-thin high-k gate dielectrics. We focus on a surprising finding that the effective capture cross-sections seemed to be extraordinarily small (between 10e-22 and 10e-19cm2) compared. We arrived at the conclusion that the low values of the effective capture cross-section arise from significant de-trapping, which is not accounted for in the trapping models used in extracting the trap cross-sections. The results of this study point out that it is important to consider the film thickness and leakage current when extracting capture cross-sections in ultra thin gate dielectrics.

Determination of the Gate Dielectric Capacitance of Ultrathin High-k Layers

A technique is proposed for extraction of the capacitance of ultrathin high-k gate dielectrics. The only assumptions made in deriving the mathematical relations for the extraction plots are that both the space charge and the interface trap capacitances are exponential functions of where is the surface potential. Deviation of the value of the constant β from that of may be considered an indication of the extent of quantization. The proposed technique, and for the sake of comparison, some existing gate dielectric capacitance extraction techniques, were applied to different high-k gate dielectrics with varying band offsets and equivalent oxide thickness (EOT) varying between 0.5 and 1.5 nm. The experimental capacitance-voltage data were taken from the literature, after carefully selecting the high-k gate dielectrics, to obtain varying band offsets and EOTs. Very satisfactory linear fits to the data points in the extraction plots were consistently obtained in the case of the proposed technique, and the values of the gate dielectric capacitance, appear to be reasonable and consistent with the experimental values of β. The McNutt, Maserjian, and Ricco techniques were found to have serious problems. © 2004 The Electrochemical Society. All rights reserved.

Extraction of the capacitance of ultrathin high-K gate dielectrics

A new technique has been proposed for the extraction of the capacitance of the ultrathin high-K gate dielectrics C/sub di/. The only assumptions made in deriving the mathematical relations for the extraction plots are that, in the accumulation regime, both the space charge and the interface trap capacitances are exponential functions of /spl beta//spl phi//sub s/, where /spl phi//sub s/ is the surface potential. The deviation of the value of the constant |/spl beta/| from that of q/2kT may be considered an indication of the extent of quantization. The proposed technique, and for the sake of comparison, some existing gate dielectric capacitance extraction techniques, were applied to different high-K gate dielectrics. The experimental capacitance-voltage ( C-V) data were taken from the literature, after carefully selecting the high-K gate dielectrics, to obtain varying band offsets and equivalent oxide thickness (EOT). Satisfactory linear fits, to the data points in the extraction plots, were obtained consistently in the case of the proposed technique, and the values of the gate dielectric capacitance C/sub di/, appear to be reasonable, and consistent with the experimental values of /spl beta/. While the classical value of |/spl beta/| is 19.38 V/sup -1/ at 300 K, the experimental value of |/spl beta/| varied from 15.31 V/sup -1/ in the case of an La/sub 2/O/sub 3/ gate dielectric with EOT = 0.47 nm to 5.77 V/sup -1/ in the case of an Al/sub 2/O/sub 3/-HfO/sub 2/ laminate gate dielectric with EOT = 1.95 nm. The McNutt, Maserjian, and Ricco techniques were found to have significant problems. The extraction plots were nonlinear in the case of both the McNutt and the Maserjian techniques; different linear fits could be made to different parts of the accumulation region, leading to multiple and/or improbable values for the gate dielectric capacitance. The Ricco factor had multiple zeros, leading to the same consequence. In addition to C/sub di/, and an experimental quantization index /spl beta/, the proposed technique also yields an experimental /spl phi//sub s/ versus bias for the accumulation regime.

Using Anodization to Oxidize Ultrathin Aluminum Film for High-k Gate Dielectric Application

Very low cost room-temperature process to fabricate ultrathin high-k gate dielectrics with equivalent oxide thickness of 10 to 35 Å was studied in this work. Anodic oxidation (anodization) in deionized water followed with rapid thermal annealing was used to oxidize ultrathin aluminum film. Unlike thermal oxidation, anodic possesses a speciality of self-limited oxide thickness. This work also demonstrated that the anodic exhibits gate dielectric quality characteristics, including low gate leakage current, low interface states, and low bulk trap density. The dielectric constant of anodic is estimated to be 9.7. In addition, the gate current density, is almost independent of the measurement temperature, revealing a low trap density and high thermal stability. These good insulator characteristics are believed to be related to the leakage path self-readjustment nature under electric field influence in liquid during anodization. © 2003 The Electrochemical Society. All rights reserved.

Alternating Layer Chemical Vapor Deposition (ALD) of Metal Silicates and Oxides for Gate Insulators

ABSTRACTA new process was developed for deposition of the silicates and oxides of metals such as zirconium and hafnium at low substrate temperatures (100–300°C). The silicon and oxygen source is tris(tert-butoxy)silanol, (tBuO)3SiOH, and the metal precursors are metal amides. A typical reaction isZrL4 + 2 (tBuO)3SiOH → ZrSi2O6 + 4HL + 6H2C=C(CH3)2 + 2 H2Oin which the ligand L is ethylmethylamide, -NEtMe. The precursor vapors were alternately pulsed into a heated reactor, yielding about 0.3 to 0.7 nm of metal silicate film for each cycle. Replacing the silanol pulses with water pulses yields pure metal oxides with a thickness of about 0.1 to 0.15 nm per cycle. The silicon content of the films can be adjusted to any desired value by replacing some of the silanol pulses by water pulses. This new process has a number of advantages over previous methods for depositing metal silicates. Uniformity of thickness and stoichiometry are readily achieved. The deposition atmosphere is non-oxidizing, so that formation of low-k interfacial oxides between the deposited layer and a silicon substrate is minimized. The new halogen-free precursors avoid halogen contamination of films and corrosion of deposition systems. This process is a promising method for forming the next generation of ultra-thin high-k gate dielectrics in silicon-based microelectronics.