Ultralow-k Layers Research Articles

Top-down delayering to expose large inspection area on die side-edge with Platinum (Pt) deposition technique

The shrinking in feature sizes of semiconductor devices from integrated circuit (IC)11Integrated circuit (IC). and function complexity has led to greater PFA22Physical Failure Analysis (PFA). delayering challenges. The challenges stem from incorporation of top thick hard Silicon Dioxide (SiO2) material that is formed from Tetra Ethyl Ortho Silicate (TEOS)33Tetra Ethyl Ortho Silicate (TEOS). as Inter-Metal Dielectric (IMD)44Inter-Metal Dielectric (IMD). and very thin ultra low-k dielectric material.For a device in copper (Cu) metal line technology, it is almost impossible to expose the entire layer at the same surface flatness by using a conventional top down polishing method, especially at the interface on TEOS and ultra low-k layer where die's side-edge is always thinner than die center (edging effect). Hence, for cases that required PFA delayering on the die side-edge especially for those packaged device or skeleton die, it is extremely challenging for PFA skillset.This paper outlines a proposed technique; perform Platinum (Pt) deposition on the selective area to slow down the side-edging effect. This proposed technique is easy and less skillset dependent to deprocess sample for defect identification analysis.

Chip Packaging Interaction (CPI) with Cu Pillar Flip Chip for 20 nm Silicon Technology and Beyond

Chip packaging interaction (CPI) has drawn great attention to advanced silicon technology nodes due to the introduction of Low-K (LK) and Ultra Low-K (ULK) materials in back end of line (BEOL) and Cu pillar in chip package interconnects. This paper summarizes GLOBALFOUNDRIES's activities in CPI studies for the 20 nm technology node, which includes CPI structure design, BEOL process characterization and optimization, assembly process optimization and reliability tests. The key issues and challenges were identified, analyzed, and overcome through a Design of Experiment (DOE) study in BEOL Q-time and reflow parameters in assembly process. It has been found that 1) BEOL ULK layer Q-time before SiCN capping is critical for moisture diffusion into BEOL materials, which affects both electrical performance and reliability; 2) Reflow temperature plays key role to control the package warpage to avoid non-wet issue. Package level reliability evaluation was performed and the results were reported. Through this study, it has been demonstrated that GLOBALFOUNDRIES's 20 nm technology successfully passed all CPI reliability tests. CPI challenges for future technology nodes and emerging packaging integration solutions are also discussed in the paper.

An RDL UBM Structural Design for Solving Ultralow-K Delamination Problem of Cu Pillar Bump Flip Chip BGA Packaging

Copper (Cu) pillar bumps tend to induce high thermal–mechanical stress during environmental tests and fabrication processes due to the high hardness of Cu, especially when applied with an ultralow-K (ULK) chip. A previous experiment showed that interfacial delamination was often observed in the ULK layers of conventional Cu pillar bump-type flip chip ball grid array (FCBGA) packages under thermal cycling, where under bump metallurgy (UBM) layers directly sit on the metal pads of silicon chips (herein termed ‘‘direct UBM structure’’). In this study, a UBM pad relocation scheme through redistribution layer (RDL) technology (herein termed ‘‘RDL UBM structure’’) is proposed to relieve the stress or ULK delamination issue. The proposed technique is tested on Cu pillar bump-type FCBGA packages subjected to thermal loading, the effectiveness of which is demonstrated through finite element stress simulation and experimental reliability tests. Simulation results reveal that the RDL UBM structure can greatly reduce the maximum stress in the ULK layers by as much as about 10% to 44%. Besides, it turns out that the Cu pillar bump-type FCBGA packages with the RDL UBM structure show good interconnect reliability performance in terms of thermal cycling, highly accelerated stress, and high-temperature storage.

Study of Chip–Package Interaction Parameters on Interlayer Dielectric Crack Propagation

To meet the electrical performance requirements, copper traces with ultralow- k (ULK) interlayer dielectric (ILD) materials are used in today's semiconductor devices. The dielectric constant (k) of these materials is often reduced through the introduction of pores or inclusions, and thus, the ULK ILD materials have low fracture strength. During flip-chip assembly, thermally induced stresses occurring due to the differential displacement between the substrate and the die can result either in ILD cracking or in ILD delamination in the vicinity of solder bump. Such reliability problems are a cause for concern in semiconductor devices. In this paper, we study such dielectric cracking through numerical models and experiments and present methods to reduce such dielectric cracking. This work uses a finite-element-based submodeling approach to study ILD cracking in flip-chip assemblies. The developed “global” model accounts for the die, the passivation layer, the die pad, the solder bump, the substrate pad, and various layers in the substrate, including the trace pattern effective directional modulus. The displacement boundary conditions from the global model under flip-chip assembly cooling are then applied to a “local model,” which accounts for the die with its backend-of-line (BEOL) stack details, such as the die pad, the passivation layer, the solder bump, the substrate pad, and layers in the substrate. The local model focuses on the most critical solder bump, based on global stress contours. Next, cohesive cracks are introduced at various locations in the ULK layers above the critical solder bump and are allowed to propagate under flip-chip assembly reflow thermal conditions. It can be seen that the elastic energy available for crack propagation initially increases with crack length, but then starts to decay, indicating that the ILD cracking is often confined in the vicinity of one bump. Furthermore, the results from the models have been compared against experimental failure analysis results of 45-nm (C45) devices. It is also shown that the models can provide geometry and material guidelines to reduce ILD cracking.

New generation of reactive pre-clean prior to barrier–seed deposition to preserve ULK integrity

Advanced interconnects development requires introduction of porous ultra low k (ULK) dielectrics enhancing product performance through parasitic capacitance reduction. ULK layers are characterized by higher carbon content and lower mechanical properties due to porosity increase. Consequently, ULK dielectrics are more prone to be damaged during plasma treatment in interconnects build [1]. Pre-clean processes prior to barrier/seed deposition are a potential area of concern for ULK integrity. Reactive pre-clean processes based on He/H2 plasma are investigated in this paper through two types of hardware. The new pre-clean chamber is an upgrade of conventional pre-clean hardware and combines optimized H2 plasma and active wafer temperature control to ensure efficient copper oxide reduction [3] and via cleaning. The aim of the paper is to evaluate performance of the new generation of reactive pre-clean compared to conventional hardware. To overcome ULK dielectric integration challenge, pre-clean processes need to ensure efficient copper oxide reduction and via bottom cleaning with minimum impact on ULK material properties. The ''new reactive pre-clean'' addresses these requirements for k=2.5 ULK materials. The new reactive pre-clean demonstrates a robust process window over a wide range of temperature and pressure settings for all characterized aspects. The ''new reactive pre-clean'' technology is seen to be a promising pre-clean candidate for next generation of porous ULK dielectric material ([email protected]?2.5) integration for 28nm node and beyond.

Profiling of the Mechanical Properties of Ultralow-k Films Using Nanoindentation Techniques

ABSTRACTSeveral nanoindentation techniques were applied to the surface, the reverse side and cross-sections of PECVD ultralow-k (ULK) film stacks to characterize their elasto-plastic properties quantitatively. Results showed good agreement of the reduced modulus (Er) values measured from above and on cross-sections, respectively. Er decreased by 10-22% from the upper to the lower surface of the films. This gradient suggests that UV light absorption inside the film leads to slightly reduced curing at the rear side of the films compared to the surface of the ULK layers. Both quasi-static nanoindentation and dynamic mechanical mapping showed this trend. It is demonstrated that quantitative mechanical mapping can be performed with a lateral resolution ≤ 100nm. Slight local variations of Er were detected on ULK/SiCxNy films stacked on top of Cu-low-k interconnect structures.

Fracture Toughness Assessment of Patterned Cu-Interconnect Stacks by Dual-Cantilever-Beam (DCB) Technique

Dual cantilever beam (DCB) mechanical testing is applied to two kinds of chips, manufactured in the 45 nm technology node. Both chips consist of different numbers of ultra low-k (ULK) dielectric layers, however, they have similarly designed crack-stop structures. It is shown that in all cases, cohesive cracking occurred in the upper ULK layers. The crack-stops hamper the crack propagation, and cracks are deflected outside the interconnect stack. The paths of the deflected crack fronts are FIB-sectioned and imaged in SEM. The increasing number of ULK layers leads to decrease in effective <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Gc</i> of the stack.

Surface properties restoration and passivation of high porosity ultra low- k dielectric ( k ∼ 2.3) after direct-CMP

Surface hydrophilisation and effective k-value degradation have been reported in literature after direct-CMP of high porosity SiOC films (without a protective capping layer). In the sequel, attempts to restore ultra low- k (ULK) material initial properties after a standard CMP and post-CMP cleaning process are reported. Annealing treatment has shown to be valuable to remove residual organics and water absorbed at the ultra low- k material surface after direct-CMP. However, as the hydrophilicity of the polished surface remains unchanged, it does not prevent moisture uptake, leading to an increase in k-value with time. Therefore, in order to restore hydrophobic properties and to stabilize the surface in time, three silylating agents – containing chlorosilane reactive groups (–SiMe n Cl 3− n ) as well as hydrophobic methyl functions (–CH 3) in their structure – have been employed in liquid, gas or dense CO 2 phases on the CMP-induced damaged ULK layers. While each of these organic treatments is efficient to restore hydrophobicity on post-CMP ULK surfaces, only one of them proved to be able to keep the k-value low (comparable to the ULK pristine k-value) and stable in time, without inducing significant change in porosity of the ULK material.

Development of a permittivity extraction method for ultra low k dielectrics integrated in advanced interconnects

An extraction method to determine the permittivity of ultra low k (ULK) dielectrics on real integrated structures is presented. It is a two-step method based on a comparison between measured and simulated capacitance. A best-estimate value of the k ULK value is first extracted with optimization software coupled to capacitance extraction software. Secondly, uncertainties on material and process parameters are considered to determine an error margin on the best-estimate extracted k value. The uncertainty on the best-estimate value is approximated by a function of the uncertainties on material and process variables. This function is calculated using a multi-linear approximation model and a numerical design of experiments. The same method is applied for the extraction of a ULK material k value ( k ULK) value and an effective k value ( k eff) but with two different simulation structures. In the simulation structure used for k eff extraction, an equivalent dielectric layer including the ULK layer, the etch-stop and capping layers is used. This method was applied to metal 1 single damascene structures. First results of extraction are presented for two different ULK dielectrics. With the estimated uncertainty used for the parameters in this work, the uncertainties obtained for the best-estimate value of k ULK and k effective are significant. Due to the linearity of the model, the method is still applicable with different values for parameters uncertainty. An analysis work will be realized to improve the parameters uncertainty estimation. Future work will also include extraction of ULK permittivity for more complex structures like double damascene structures.

Damage of ultralow k materials during photoresist mask stripping process

Plasma-based ashing of photoresist masks after pattern transfer is a common processing step in the fabrication of integrated circuits. In this work we investigated damage mechanisms of nanoporous ultra low k (ULK) materials with different overall porosities due to the ashing process. Oxygen-, nitrogen- and hydrogen-based photoresiststripping using direct and remote plasma processes were examined. Ellipsometry, x-ray photoelectron spectroscopy, secondary ion mass spectroscopy, and transmission electron microscopy were utilized to study the damage layer thickness, physical (pore morphology), and chemical modifications of the nanoporous silica thin films after exposure to the O2-, N2- or H2-based ashing processes. As a result of the plasma exposure, carbon groups in nanoporous silica can be removed from the ULK layers which is also accompanied by material densification. We find severe ashing damage of ULK materials after O2-based ashing using both direct and remote discharges. N2 and H2 discharges also damage ultralow k materials for direct plasma ashing processes which are accompanied by low energy ion bombardment of the substrates. The introduction rate and degree of the ULK materials modifications correlates with the overall porosity. We show that the pore interconnectivity is one of the key parameters that determine ashing damage. ULK damage is greatly reduced for remote N2 or H2 discharges, but the resist removal rates are impractically low if the substrate is at room temperature. We show that both acceptable photoresist stripping rates and ULK damage levels can be achieved for remote H2 plasma ashing processes if the substrate temperature is 250°C and higher.