Ultra-low Energy Consumption Research Articles

Electric field control of the magnetic anisotropy energy of double-vacancy graphene decorated by iridium atoms.

To solve the fundamental dilemma in data storage applications, it is crucial to manipulate the magnetic anisotropy energy (MAE). Herein, using first-principles calculations, we predict that the system of double-vacancy graphene decorated by iridium atoms possesses high stability, giant MAE, perpendicular-anisotropy and long-range ferromagnetic coupling. More importantly, the amplitude of MAE can be manipulated by electric fields. This is due to the change in the occupation number of Ir-5d orbitals. The present hybrid system could be a high-performance nanoscale information storage device with ultralow energy consumption.

Accelerated Visual Context Classification on a Low-Power Smartwatch

Data produced by wearable sensors is key in contexts such as performance enhancement and training help for sports and fitness, continuous monitoring for aging people and for chronic disease management, and in gaming and entertainment. Unfortunately, wearable devices currently in the market are either incapable of complex functionality or severely impaired by short battery lifetime. In this work, we present a smartwatch platform based on an ultralow-power (ULP) heterogeneous system composed of a TI MSP430 microcontroller, the PULP programmable parallel accelerator, and a set of ULP sensors, including a camera. The embedded PULP accelerator enables state-of-the-art context classification based on convolutional neural networks to be applied within a sub-10-mW system power envelope. Our methodology enables to reach high accuracy in context classification over five classes (up to 84%, with three classes over five reaching more than 90% accuracy), while consuming 2.2 mJ per classification, or an ultralow energy consumption of less than 91 $\mu$ J per classification with an accuracy of 64%–3.2 $\times$ better than chance. Our results suggest that the proposed heterogeneous platform can provide up to 500 $\times$ speedup with respect to the MSP430 within a similar power envelope, which would enable complex computer vision algorithms to be executed in highly power-constrained scenarios.

An Ultralow-Voltage Sensor Node Processor With Diverse Hardware Acceleration and Cognitive Sampling for Intelligent Sensing

An energy-efficient sensor node processor (SNP) is presented for intelligent sensing in Internet of Things (IoT) applications. To achieve ultralow energy consumption and satisfying performance, the proposed processor incorporates an ARM Cortex-M0 RISC core and diverse hardware accelerators, including discrete wavelet packet transform engine, finite-impulse-response filtering engine, fast Fourier transform engine, and coordinate rotation digital computer engine, to accelerate signal processing tasks. At the architecture level, dual-bus architecture with automatic bus sensing and reconfigurable memory access scheme are proposed. At the circuit level, digitally assisted cognitive sampling and ultralow-voltage operation with in situ timing-error monitoring techniques are employed. When applied to neural spike classification and vehicle speed detection, the proposed SNP consumes only 39 and 29 pJ/cycle, respectively.

Current-driven dynamics of skyrmions stabilized in MnSi nanowires revealed by topological Hall effect.

Skyrmions hold promise for next-generation magnetic storage as their nanoscale dimensions may enable high information storage density and their low threshold for current-driven motion may enable ultra-low energy consumption. Skyrmion-hosting nanowires not only serve as a natural platform for magnetic racetrack memory devices but also stabilize skyrmions. Here we use the topological Hall effect (THE) to study phase stability and current-driven dynamics of skyrmions in MnSi nanowires. THE is observed in an extended magnetic field-temperature window (15–30 K), suggesting stabilization of skyrmions in nanowires compared with the bulk. Furthermore, we show in nanowires that under the high current density of 108–109 A m−2, the THE decreases with increasing current densities, which demonstrates the current-driven motion of skyrmions generating the emergent electric field in the extended skyrmion phase region. These results open up the exploration of skyrmions in nanowires for fundamental physics and magnetic storage technologies.

Modulation bandwidth and energy efficiency of metallic cavity semiconductor nanolasers with inclusion of noise effects

AbstractModulation bandwidth and energy efficiency of metallic cavity nanolasers are studied in both small signal and digital modulation formats. Special emphasis is placed on the effects of noise on data rate and energy efficiency. It is found that the data rate for nanolasers of small sizes is severely limited by noise‐induced bit‐error rate. The trade‐off between size‐reduction and noise effects leads to an optimal cavity size to achieve the highest data rate. The energy data‐rate ratio decreases in general with device size, but starts to increase in ultrasmall devices, due to increased threshold current and noise effects. However, relatively high modulation rate and energy efficiency can be achieved in metallic cavity nanolasers. Calculations show that a low energy consumption of 30 fJ/bit at a high data rate of 120 Gbit/s can be realized in nanolasers as small as V = 16 (λ/nr)3 (V is the laser cavity volume). Ultralow energy consumption per bit (<10 fJ/bit) does require smaller devices (V<2.1 (λ/nr)3), while the noise limits the data rate to below 50 Gbit/s. Such a balanced and holistic consideration between device size, data rate, noise effects, and energy efficiency offers new perspectives to nanolaser design strategy for future onchip integrated nanophotonics systems. image

A Physics-based Memristor Model Based on Chalcogenide Alloy

Memristor, as the fourth fundamental circuit element, has recently attracted considerable attention due to its widespread applications from programmable logic to neural networks. Today, the most representative memristor consists of a thin film of titanium oxide sandwiched by two electrodes. However, such a memristor gives rise to a relatively low switching speed, discouraging it from receiving more research enthusiasm. To overcome the disadvantages of the already established memristors (e.g. low switching speed and poor endurance) and thus to optimize the memristor performance, we proposed a novel memristor concept using chalcogenide alloy that has been widely used for nonvolatile memory storage. According to the developed electro-thermal model, the designed memristor using chalcogenide alloy clearly shows a variation of resistance along with the history of current as well as a fast switching speed and ultra-low energy consumption. Keywords: Cycle, chalcogenide, Ge2Sb2Te5, memristor, model.

Fundamental research and practice of passive and ultra-low energy consumption buildings

This represents a multi-task topic, because it involves several challenges arising from indoor environmental quality, building energy efficiency, and vernacular culture inheritance. Although China is proud of its vast territory and resources, it has experienced pressure from a low per-capita share of resources owing to its large population. A vulnerable ecological environment has stimulated the increase and improvement of environmentally friendly and energy-saving buildings. It is essential to inherit the vernacular culture during development of a sustainable habitat environment, rather than modifying it by building new but identical or even wacky architecture. This is an effective and widely-applicable approach to solving the above challenges, through adopting passive technology in building ultra-low energy consumption buildings. As a flexible approach, passive technology has excellent applicability in meeting demands of the environment, energy resources, and vernacular culture. This paper introduces a systematic study of passive design for ultra-low energy buildings. According to existing theory of passive design, the following two key aspects in the application of passive technology were addressed in the work. First, the feasibility of using outdoor climatic resources was investigated, to determine their upper and lower limit conditions for indoor heating and cooling, respectively. The second aspect is the development and optimization of building design strategies with the use of passive technology, to effectively use the heating and cooling capacity of outdoor climate. The fundamental concept of passive and ultra-low energy building design was conducted from these two aspects. The critical and most valuable contribution of this research is the reduction of building energy consumption by decreasing the demand for artificial heating and cooling facilities. This can be achieved by effectively narrowing the difference between human thermal comfort and outdoor climate, and enlarging the climatic interval size that the passive design technology is able to control. Regarding the practice of passive and ultra-low energy consumption buildings, through a combination of theoretical, experimental, in - situ and statistical analyses involving multiple disciplines such as architecture, building climatology and building environment engineering, we determined the regular pattern of human thermal comfort under natural climate fluctuation. We also developed a bioclimatic analysis tool based on the human thermal comfort demands, and climatic zones for passive design were defined accordingly. A thermotechnical calculation for passive solar heating design and a simplified indoor temperature calculation for nocturnal ventilation are proposed. These capabilities can quantitatively analyze problems in the “Human-Architecture-Climate” system. The proposed concepts and theories have been successfully applied to Western China, the Loess Plateau, an arid area of northwest Yinchuan, and the Sichuan earthquake zone. This work spreads the knowledge of passive technology and provides flagship models for further study.

(Invited) Ultralow-Voltage Design and Technology of Silicon-on Thin-Buried-Oxide (SOTB) CMOS for High Energy Efficient Electronics in IoT Era

We demonstrated ultralow voltage (<0.4V) operation of Silicon-on-Thin-Buried-oxide (SOTB) CMOS. Thanks to the small variability of SOTB Vmin of SRAM was lowered down to <0.4 V. Both fast access time and small standby leakage were achieved by adaptive back biasing (ABB). 32-bit RISC CPU operated at ultralow energy consumption of 13.4 pJ.

ChemInform Abstract: Electric Field Control of Magnetism Using BiFeO3‐Based Heterostructures

AbstractReview: 106 refs.

Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation

Geometry scaling of semiconductor devices enables the design of ultra-low-cost (e.g., below 1 USD) battery-powered resource-constrained ubiquitous devices for environment, urban life, and body monitoring. These sensor-based devices require high performance to react in front of infrequent particular events as well as extreme energy efficiency in order to extend battery lifetime during most of the time when low performance is required. In addition, they require real-time guarantees. The most suitable technological solution for these devices consists of using hybrid processors able to operate at: (i) high voltage to provide high performance and (ii) near-/subthreshold voltage to provide ultra-low energy consumption. However, the most efficient SRAM memories for each voltage level differ and trading off different SRAM designs is mandatory. This is particularly true for cache memories, which occupy most of the processor's area. In this article, we propose new, simple, single-Vcc-domain hybrid L1 cache architectures suitable for reliable hybrid high and ultra-low voltage operation. In particular, the cache is designed by combining heterogeneous SRAM cell types: some of the cache ways are optimized to satisfy high-performance requirements during high voltage operation, whereas the rest of the ways provide ultra-low energy consumption and reliability during near-/subthreshold voltage operation. We analyze the performance, energy, and power impact of the proposed cache designs when using them to implement L1 caches in a processor. Experimental results show that our hybrid caches can efficiently and reliably operate across a wide range of voltages, consuming little energy at near-/subthreshold voltage as well as providing high performance at high voltage without decreasing reliability levels to provide strong performance guarantees, as required for our target market.

Electric field control of magnetism using BiFeO3-based heterostructures

Conventional CMOS based logic and magnetic based data storage devices require the shuttling of electrons for data processing and storage. As these devices are scaled to increasingly smaller dimensions in the pursuit of speed and storage density, significant energy dissipation in the form of heat has become a center stage issue for the microelectronics industry. By taking advantage of the strong correlations between ferroic orders in multiferroics, specifically the coupling between ferroelectric and magnetic orders (magnetoelectricity), new device functionalities with ultra-low energy consumption can be envisioned. In this article, we review the advances and highlight challenges toward this goal with a particular focus on the room temperature magnetoelectric multiferroic, BiFeO3, exchange coupled to a ferromagnet. We summarize our understanding of the nature of exchange coupling and the mechanisms of the voltage control of ferromagnetism observed in these heterostructures.

A low energy consumption wireless sensor network control system

As the basis of internet of things, wireless sensor network technology has been widely studied. However, currently studied wireless sensor network systems should be continuously powered and the energy consumption is big. They are not suitable for the strict low energy consumption or no continuous power supply applications. This paper presents a wireless sensor network control system based on the ultra-low energy consumption architecture. Experimental results show that the system can control all kinds of devices with very low energy consumption and it does not need continuous power supply. This indicates that the wireless control system is very flexible and convenient and can be widely used in the scenarios with strict low energy consumption requirement.

Design of a Voltage‐Controlled Magnetic Random Access Memory Based on Anisotropic Magnetoresistance in a Single Magnetic Layer

A simple and fully gate-voltage-controlled magnetic random access memory is designed based on anisotropic magnetoresistance. This multiferroic memory device consists of just a single magnetic film grown on a ferroelectric layer with bistable in-plane anisotropic ferroelastic or piezo strains induced by out-of-plane voltages. It can simultaneously achieve ultrahigh storage density, ultralow energy consumption, and GHz high-speed operation at room temperature.

Design, Analysis and Evaluation of A New Energy Conserving MAC Protocol for Wireless Sensor Networks

Low power listening (LPL) MAC protocols based on duty-cycling mechanism have been studied extensively to achieve ultra low energy consumption in wireless sensor networks (WSNs). Especially, recent ACK-based LPL schemes such as X-MAC employ strobe preambles and an early ACK, and show fair performances in communications and energy efficiencies. However, the state-of-the-art ACK-based LPL scheme still suffers from collision problems due to the protocol incompleteness. These collision effects are not trivial and make WSNs unstable, aggravate energy consumptions. In this paper, we propose two novel schemes; (i) τ-duration CCA to mitigate the collision problem in ACK-based LPL MAC protocols. (ii) Short Preamble Counter (SPC) to conserve more energy by reducing unnecessary overhearing. We demonstrate the performance improvement of our scheme via a mathematical analysis and real-time experiments. Both analysis and experimental results confirm that our proposed scheme saves energy by up to 36% compared to the naive ACK-based LPL MAC protocol thanks to τ-duration CCA and SPC.

40-Gb/s directly-modulated photonic crystal lasers under optical injection-locking

CMOS integrated circuits (IC) usually requires high data bandwidth for off-chip input/output (I/O) data transport with sufficiently low power consumption in order to overcome pin-count limitation. In order to meet future requirements of photonic network interconnect, we propose an optical output device based on an optical injection-locked photonic crystal (PhC) laser to realize low-power and high-speed off-chip interconnects. This device enables ultralow-power operation and is suitable for highly integrated photonic circuits because of its strong light-matter interaction in the PhC nanocavity and ultra-compact size. High-speed operation is achieved by using the optical injection-locking (OIL) technique, which has been shown as an effective means to enhance modulation bandwidth beyond the relaxation resonance frequency limit. In this paper, we report experimental results of the OIL-PhC laser under various injection conditions and also demonstrate 40-Gb/s large-signal direct modulation with an ultralow energy consumption of 6.6 fJ/bit.

Breakdown delay-based depletion mode silicon modulator with photonic hybrid-lattice resonator

A compact silicon electro-optic modulator that operates in the breakdown delay based depletion mode is introduced. This operation mode has not previously been utilized for optical modulators, and represents a way to potentially achieve much higher modulation speeds and carrier extraction efficiencies without sacrificing energy efficiency, which is a critical criterion for realizing miniaturized sub-THz modulation components in silicon. Our study shows a speed of at least 238 GHz modulation is achievable along with an ultra-low energy consumption of 26.6 fJ/bit in a simple planar P+PNN+ diode example structure, which is embedded in a 2D hybrid photonic lattice mode gap resonator. The optical resonator itself is only 69 µm2 in footprint and is designed for optimized electro-optic sensitivity and conversion efficiency with reduced carrier scattering. Both the static and dynamic device performance are backed up by fully integrated 3D optical and 3D electrical numerical results. The compact device dimensions and low energy consumption are favorable to high density photonic integration.

Design of a Tunable All-Digital UWB Pulse Generator CMOS Chip for Wireless Endoscope

A novel tunable all-digital, ultrawideband pulse generator (PG) has been implemented in a standard 0.18-¿ m complementary metal-oxide semiconductor (CMOS) process for implantable medical applications. The chip shows that an ultra-low dynamic energy consumption of 27 pJ per pulse without static current flow at a 200-MHz pulse repetition frequency (PRF) with a 1.8-V power supply and low area of 90 × 50 ¿m(2). The PG generates tunable pulsewidth, amplitude, and transmit (Tx) power by using simple circuitry, through precise timing control of the H-bridge output stage. The all-digital architecture allows easy integration into a standard CMOS process, thus making it the most suitable candidate for in-vivo biotelemetry applications.

Low V_pp, ultralow-energy, compact, high-speed silicon electro-optic modulator

We present a high-speed silicon optical modulator with a low V(pp) (peak-to-peak driving voltage) and ultralow energy consumption based on a microring resonator, with the refractive index modulation achieved by electric-field-induced carrier depletion in a reverse-biased lateral pn diode embedded in the ring structure. With a V(pp) of 2 V, we demonstrate a silicon modulator with a 3 dB bandwidth of 11 GHz, a modulation depth of 6.5 dB together with an insertion loss of 2 dB, ultralow energy consumption of 50 fJ per bit, and a small device active area of approximately 1000 microm(2).

Electro-optic polymer assisted optical switch based on silicon slot structure

One kind of electro-optic polymer assisted Mach–Zehnder optical switch based on silicon slot structure is presented in this paper. The interference arms of the switch are slot structures instead of regular single-mode waveguides. By filling electro-optic material in the void slot of the arms, direct electro-optic modulation can be introduced. Theoretical model and detailed analysis are given in this paper. The length-independent product V πL is about 74 mV cm when slot width is 100 nm, and 37 mV cm when slot width is 50 nm, when the polymer with a electro-optical coefficient of γ 33 = 130 pm/V is assisted. An ultralow energy consumption of only 37 fJ/bit is achievable, and the turn-on time of the switch is less than 1.5 ps.

High Performance Ge Devices for Electronic-Photonic Integrated Circuits

We present high performance, Ge-based photodetectors and electro-absorption (EA) modulators for electronic-photonic integrated circuits on Si platform. As a pseudo-direct band gap material, Ge offers excellent optoelectronic properties with CMOS compatibility. We demonstrate waveguide-integrated Ge photodetectors with a high responsivity of >1.0 A/W in a broad spectrum range of 1470-1570 nm and >7 GHz bandwidth at a low reverse bias of -0.1 V. We have also achieved a waveguide-integrated, ultra-low energy GeSi EA modulator with a small footprint of 30 µm2, a 10 dB extinction ratio at 1540 nm, an ultra-low energy consumption of 50 fJ/bit, and an operation spectrum that covers half of the C-band. These devices have been fabricated with standard CMOS technology and can be conveniently integrated with CMOS circuits for electronic-photonic integration.