Ultra-high Speed Data Acquisition Research Articles

Researches on Channel Mismatch Effects in Time-Interleaved ADC System

The Time-Interleaved ADC（TIADC) is an effective method for implement ultra high-speed data acquisition. However, the errors of channel mismatch are seriously degrade the signal-to-noise ratio of the system, such as Time-skew error, Gain error and Offset error. This paper have done some researches and analysis, and given the modeling of the three channels mismatch. What's more, it also given a detailed analysis of error and the method of measure it, derived the formula of signal to noise and distortion ratio(SINAD) and spurious free dynamic range(SFDR). All of them provide a reference for the tolerance range of TIADC channel mismatch error. Meanwhile, the result of this paper has provided a theoretical basis for eliminating TIADC channel mismatch error.

Research on Wideband Guiding System Receiving Technology

The ultra-high speed data acquisition system is introduced, which has sampling rate of 3GSPS. The design scheme of hardware circuit is given in condition to analyze the theory and technology of signal sampling. The design of the main part circuit is described. The module of serial -parallel conversion and FFT spectrum analysis are designed in software realization. The system has strong commonality because of application of the ADC + FPGA + DSP framework.

Integrated Instrument of Ultra-High Speed Data Acquisition and Storage

Along with the rapid development of computer technology, high speed data acquisition and storage system has been widely applied in plenty of engineering fields, such as radar, aerospace industry, communication, etc. In order to satisfy the increasing requirement, we present the design structure of a novel integrated instrument for ultra-high speed data acquisition and storage, which is composed of ultra-high speed data acquisition, high speed data transmission and solid storage three main sub-systems. The detailed design and realization of the sub-systems are presented. We test and analysis the performance of the integrated instrument and the actual results show that the instrument performs stably and provides excellent speed and precision.

Snapshot sampling for ultra-high speed data acquisition

A snapshot sampling technique is presented, which uses an optimised inverter chain for sample control and a simple sample-and-hold-circuit for highest speed and low current consumption. Simulations indicate a data acquisition time of 0.34 ns for a simple 0.8 µm digital CMOS process.