Ultra-fine Pitch Interconnects Research Articles

Compliant Interconnects Based on Single Micrometer-sized Metal-Coated Polymer Spheres.

The rapid evolution of multifunctional electronics necessitates interconnection technologies appropriate for large dies with high-density and/or ultrafine pitch input/output pins. Existing technologies face numerous challenges, including demands for bonding equipment that can deliver extremely high force as well as thermo-mechanical stresses induced in the assembled packages due to mismatched thermal expansion of materials involved. This study proposes an approach to compliant interconnects comprising single micrometer-sized metal-coated polymer spheres, being joined to mating electrodes by sintering of Ag nano ink at low temperature (140 °C) and low pressure (∼15 mN/particle). Such an interconnection technology is expected to enhance the thermo-mechanical robustness of the assembled packages as well as be capable of high-density, ultrafine pitch interconnects. Our approach demonstrates control over conductive particles during assembly, achieving a 98% success rate in individual interconnects with a single captured particle. The use of sintered Ag not only secures free-standing particles on electrical pads (with an adhesion force above 2 μN) but also results in a 15% reduction in interconnect resistance, with measured resistance as low as 0.5 Ω, compared to interconnects without Ag ink. This method presents an alternative to metallurgical joints, particularly suited for high-density, ultrafine pitch applications, offering low bonding pressure and temperature, along with improved interconnect compliance to enhance the thermo-mechanical robustness of the packages.

Electroless deposition of high-uniformity nickel microbumps with ultrahigh resolution of 8 μm pitch for monolithic Micro-LED display

Micro-light-emitting diode (Micro-LED) displays have attracted growing attention due to their unsurpassed properties that satisfy the requirements of reality/virtual reality (AR/VR) displays. A crucial procedure of monolithic integration technology in high-density microdisplays is the interconnection process, which is intimately associated with the quality of the display device. Microfluidic electroless interconnection (MELI), an innovative low-temperature and pressure-free chip-stacking approach that eliminates the warpage-induced issues and cracking damage of the chip caused by thermo-compression bonding (TCB), holds great promise as a technology for establishing interconnections between the CMOS driver and Micro-LED. However, the requirement for the consistency of the microbump arrays and the risk of creating bridges is significantly intensified with smaller gaps in stacked chips, which restricts the application range of MELI to high-density interconnects. This paper analyzes the feasibility of further lowering the stand-off height of stacked chips in ultrafine pitch interconnects by optimizing the bump preparation process. The plasma modification time and surfactant concentration during the bump preparation process have been investigated. The result indicated that microbump arrays with a uniformity of less than 3% could be successfully manufactured by employing a 7-min plasma treatment and incorporating optimal surfactants, which catalyzes the implementation of the subsequent vertical interconnection process and eventually enhances yields of Micro-LEDs.

Growth behavior and mechanism of atomic layer deposition of Ru for replacing Cu-interconnects

The growth behavior and nucleation mechanism of Ru films on various substrates using Ru(EtCp)2 as the precursor and O2 as the reactant were studied systematically. The results show that the Ru films grow rapidly on TiN substrates with almost no incubation time. Different of the segregation and combustion mechanism reported in the previous literature, we established the adsorption and combustion mechanism of ALD-Ru on TiN substrates. SEM and XPS confirmed that the grown Ru films were polycrystalline (average grain size of 16.53 nm, negligible impurities). The Ru films annealed at 600 °C showed significantly low resistivity of 9.73 μΩ•cm, which is one of the lowest resistivities reported in the literature so far. Suppressing electron scattering at grain boundaries is crucial factor to preparing Ru films with low resistivity. The work uses a simple plasma-free technique to construct high-quality Ru films with extremely low resistivity and low impurities, making them one of the ideal candidates for replacing Cu in future ultrafine-pitch interconnects. Furthermore, the work is significant for understanding the growth behaviors and nucleation mechanisms of Ru films on different substrates.

Atomic fast dynamic motion on the Cu nanoparticle’s surface before melting: A molecular dynamics study

The Cu nanoparticle solder owns a broad potential application prospect for the ultra-fine pitch interconnection. It is reported that the Cu nanoparticles can be sintered at about 500–600 K, which is only about 40% of the bulk melting point. The extremely low temperature sintering is generally thought to be caused by the surface melting of the nanoparticle. We perform a simulation on the Cu nanoparticle via molecular dynamic simulation, and find that the surface melting is insufficient to cause the low temperature sintering. An unusual atomic fast dynamic motion is observed on the surface of nanoparticles at about 500–600 K. The atoms on the nanoparticle's surface jump between lattice positions contributing to an extremely high diffusivity. It plays a crucial role when nanoparticles sinters at a low temperature. Further investigations show that the fast dynamic motion strongly depends on the high atomic potential energy and local atomic arrangement on the surface, which is even more vigorous at the sintering neck. The effect of the heating rate and the nanoparticle’s curvature on the fast dynamic motions are discussed further. Our study reveals the atomic mechanism on the nanoparticle's surface in low temperature conditions and provides a deep understanding of the low temperature sintering.

Directed Self-Assembly based Interconnect Technology for Next-Generation 2D/3D LSI

Three-dimensional integrated circuits (3D ICs) contain multiple layers of active device chiplets and have the potential to improve signal transfer and the overall performance of a microelectronic systems, while saving energy. Dr Takafumi Fukushima is an Associate Professor based in the Department of Mechanical Systems Engineering, Tohoku University, Japan, whose research revolves around 3D/heterogeneous/flexibel integration technologies. Within the Department Fukushima focuses on self-assembly technologies. 'Self-assembly is the process by which an organised structure spontaneously forms from individual components, as a result of specific, local interactions among the components,' he explains. One of these is advanced DSA. This process enables ultrafine-pitch interconnect formation through the simple coating and heating of nanocomposites with block co-polymers and metal compounds/nanoparticles. 'DSA is a type of directed assembly which utilises the nano-phase separation of block co-polymers to create ultrafine lines, space and hole patterns, facilitating more accurate control of the feature shapes,' Fukushima outlines. 'Conventional DSA with the block co-polymers is an alternative way to photo-patterning with photoresists that are spin-on photosensitive materials to photolithographically form fine patterns and traditionally used in semiconductor industry.' Through his advanced DSA Fukushima is able to make both ultrafine patterns as well as form lateral and vertical interconnections with nanocomposites based on non-photolithographic methodology.

A Study on the Magnetic Dispersion of the Conductive Particles of Anchoring-Polymer-Layer Anisotropic Conductive Films and Its Fine-Pitch Interconnection Properties

As the display resolution has been rapidly increased, the pitch between two electrodes has been continuously decreased to less than $20~\mu \text{m}$ pitch. Therefore, fine-pitch interconnection technology has become very important in display technology. In our previous research results, anchoring polymer layer (APL) structure was successfully introduced into anisotropic conductive film (ACF) system to form fine pitch interconnection by suppressing the conductive particles movement during the ACF assembly. In general, the agglomerated conductive particles between two electrodes can cause short-circuit problems at ACF assembly. In this paper, the magnetic field was applied to the Ni-coated polymer conductive particles in the polyvinyl fluoride (PVDF) APL structure to disperse the conductive particles uniformly in the xy plane. Then the effects of the magnetic fields on the dispersion of the Ni-coated conductive particles in the PVDF APL structure and the characterization of fine-pitch chip-on-glass (COG) assembly using PVDF APL ACFs with magnetically dispersed conductive particles were investigated. By optimizing the magnetic fields on the PVDF APL structure, 80% dispersed particle rate was successfully obtained. After the ACF bonding process, the conductive particles capture rates and contact resistance properties of magnetically dispersed PVDF APL ACFs, and the PVDF APL ACFs with no magnetic field applied were investigated at 20- $\mu \text{m}$ -pitch COG applications. Both PVDF APL ACFs showed a similar capture rate of conductive particles and electrical insulation property at $20~\mu \text{m}$ pitch. The PVDF APL ACFs with no magnetic field applied showed 100% of insulation property at $20~\mu \text{m}$ , but short circuits at less than pitch. However, for less than 20- $\mu \text{m}$ pitch, only the PVDF APL ACFs with magnetically dispersed conductive particles showed 100% insulation circuit rate down to the 11- $\mu \text{m}$ pitch because the conductive particles were not agglomerated but existed as single particles, resulting in no electrical short between fine-pitch adjacent bumps. As a result, magnetically dispersed PVDF APL ACFs can be used as new ACF materials for ultrafine-pitch interconnection applications without any electrical short.

Effects of the Nylon Anchoring Polymer Layer on the Conductive Particle Movements of Anisotropic Conductive Films for Ultrafine Pitch Chip-on-Glass Applications

Electronic packaging technology has become very important in electronic devices, because electrical interconnection problems such as high contact resistance and short-circuit failure have become serious issues in ultrafine pitch interconnection. In this paper, a nylon anchoring polymer layer (APL) structure has been introduced into the anisotropic conductive films (ACFs) system. Then, the effects of nylon APL properties on conductive particle movement of ACFs and its interconnection stability for ultrafine pitch chip-on-glass (COG) applications were investigated. The APL structure can significantly suppress the particles' movement for ultrafine pitch COG applications, and prevent the short-circuit problem between neighboring electrodes. After ACFs bonding process, the conductive particles capture rate of the conventional ACFs was 33%; however, that of the nylon APL ACFs showed 90%. In addition, the nylon APL ACFs showed excellent electrical interconnection properties such as stable contact resistances without any open or short-circuit failures. As a result, the nylon APL ACFs can be used as new interconnection materials for ultrafine pitch interconnection applications.

Latest advancement of fully additive process for 8 µm ultra-fine pitch chip-on-film (COF) by nano-size Ni–P metallization

This paper presents the first demonstration of a precision formation of conductor patterns as fine as 8 µm pitch for flex-based electronics assemblies. We have developed a novel fully additive process (FAP) by combining an ultra-thin chemical surface modification on polyimide (PI) to achieve a uniform Ni–P metallization and subsequent high-speed electrolytic pattern copper plating. On top of the modified interface, an ultra-thin anchoring layer (< 5 nm) constituting amide and carboxyl bonding is able to compensate the hydrophilic nature of the modification layer to obtain reliable adhesion even after being subjected to 300 °C heat treatment, as verified by XPS and TEM analysis at 1000kX. This exceptional property eliminates the trade-off concern by achieving both high-speed signal transmission and enhanced interfacial bond strength on a smooth surface (Ra < 60 nm). Experimental results revealed that the bending endurance and trace deformation characteristic of the fine pitch circuit by this FAP is comparable to conventional COF substrates and is also able to produce high-quality diffusion bonds with the formation of nano-twin structure on the Au–Au bonding interface. Insulation resistance measurements showed no metal residues and no current leakage between 16, 20, and 25 µm pitch COF after temperature humidity bias. On the basis of these results, FAP by direct Ni–P metallization proposed in this work provides unique opportunities for ultra-fine pitch and high electrical performance interconnects.

Addressing Flux Dip Challenges for 3-D Integrated Large Die, Ultrafine Pitch Interconnect

The requirement for closely coupled, highly integrated circuits in the semiconductor industry has spawned alternative packaging innovations such as 2.5-D/3-D integration. The incredible potential of this alternative comes with great challenges, not the least of which is the unprecedented reduction in package interconnection pitch. Market acceptance of new fine-pitch microelectronic products is strongly dependent on the development of flawless assembly processes that align with the traditional Moore-like expectation of higher performance without cost penalty. One such process is the application of flux to the interconnect surfaces to achieve effective joining. Insufficient flux quantity or flux activity can impede the formation of solid, reliable joints, whereas excessive quantities or activity can cause solder bridging or difficulties with downstream operations such as residue cleaning or underfill reinforcement. This delicate balance, already complex for traditional chip joining, is further challenged by the geometrical and spatial reductions imposed by pitch miniaturization, especially where large die, with over 100,000 interconnects, are concerned. This article presents an overall development protocol to evolving a flux dipping operation to production-level thermocompression assembly of large die (8 × 11 × 0.780 mm) with 11,343 ultrafine pitch (62 μm) copper pillar interconnections. After reviewing the state of the art for fluxing technology and detailing the specific technical issues, we present and defend the chosen flux application approach with its corresponding parameters of interest. Physical and chemical characterization results for selected flux material candidates are reported in conjunction with an analysis of how their properties correlate to the flux dip application parameters. As part of this fundamental understanding, we investigate and report on flux dip coating behavior and how it compares to other industrial dip coating applications. Finally, the results of process assembly experiments in a production-type environment are reviewed and discussed with respect to the previous characterizations. These experiments span downstream assembly process compatibility (i.e., cleaning and underfill) as well as product reliability.

Addressing Flux Dip Challenges for 3D Integrated Large Die, Ultra-fine Pitch Interconnect

Abstract The requirement for closely coupled, highly integrated circuits in the semiconductor industry has spawned alternative packaging innovations such as 2.5D/3D integration. The incredible potential of this alternative comes with great challenges, not the least of which is the unprecedented reduction in package interconnection pitch. Market acceptance of new fine-pitch microelectronic products is strongly dependent upon the development of flawless assembly processes that align with the traditional Moore-like expectation of higher performance without cost penalty. One such process is the application of flux to the interconnect surfaces in order to achieve effective joining. Insufficient flux quantity or flux activity can impede the formation of solid, reliable joints, while excessive quantities or activity can cause solder bridging or difficulties with downstream operations such as residue cleaning or underfill reinforcement. This delicate balance, already complex for traditional chip joining, is further challenged by the geometrical and spatial reductions imposed by pitch miniaturization, especially where large die, with over 100,000 interconnects, are concerned. This paper presents an overall development protocol to evolving a flux dipping operation to production-level thermocompression assembly of large die with ultra-fine pitch (60 μm) copper pillar interconnections. After reviewing the state of the art for fluxing technology and detailing the specific technical issues, we present and defend the chosen flux application approach with its corresponding parameters of interest. Physical and chemical characterization results for selected flux material candidates are reported in conjunction with an analysis of how their properties correlate to the flux dip application parameters. As part of this fundamental understanding, we investigate and report on flux dip coating behaviour and how it compares to other industrial dip coating applications. Finally, the results of process assembly experiments in a production-type environment are reviewed and discussed with respect to the previous characterizations. These experiments span downstream assembly process compatibility (i.e. cleaning and underfill) as well as product reliability.

Nanowire-Based Anisotropic Conductive Film: A Low Temperature, Ultra-fine Pitch Interconnect Solution

Advanced microelectronics packaging, driven by the multiple benefits of system performance, power, size, and cost, has now entered the three-dimensional (3-D) era. According to the International Technology Roadmap for Semiconductors 2012 [1], the interconnect pitch size is predicted to be 4?16 ?m at the global interconnect level by the year 2018. Silicon die incorporated with through-silicon-via (TSV) technology [2] can be stacked using solder microbumps as high-density interconnects [3]. However, solder microbump technology faces many challenges because of the intermetallic compound growth and an underfill requirement as the bump size reduces [4]. Meanwhile, the temperature of the soldering process is more than 260 ?C, which can result in high thermal stress in the devices and impact the thermal budget of the processing, particularly for the multitechnology node-stacking processes [5]. Therefore, developing interconnect methods, which can provide ultrafine-pitch capability and low-temperature process for 3-D systems, attracts continuous attention from industry [6].

Highly Reliable and Manufacturable Ultrafine Pitch Cu–Cu Interconnections for Chip-Last Embedding With Chip-First Benefits

Flip-chip packaging of Ultrafine pitch integrated circuits aggravates the stress-strain concerns as the interconnection pitch is decreased, requiring a fundamentally different system approach to interconnections, underfill processes and interfaces, and the substrate. This paper demonstrates an innovative and manufacturable solution to achieve excellent reliability at Ultrafine pitch (~30 μm) using direct copper-copper (Cu-Cu) interconnections with adhesives. A number of 30-μm bump pitch test vehicles (TVs) were designed with 3 mm × 3 mm chips to extract both daisy chain resistance and single-bump resistance data. Assembled bump resistivity was found to be ~ 3-4× lower than most solders. Performance of these TVs was studied for high temperature storage (HTS) life test, unbiased-highly accelerated stress test (U-HAST) and thermal cycling test (TCT). Test results showed that the assemblies with this next generation interconnection technology depicted excellent reliability results in HTS, U-HAST, and TCT tests. Based on these results, it is concluded that adhesive materials, provide unique opportunities for Ultrafine pitch and high performance interconnections.

Development of a Novel Compliant-Bump Structure for ACA-Bonded Chip-on-Flex (COF) Interconnects With Ultra-Fine Pitch

The demand for high-density electronic applications is growing. This work develops a novel chip-on-flex (COF) package with sidewall-insulated Au-coated polyimide (PI) compliant-bumps. A double-layer anisotropic conductive adhesive (ACA) material that meets the assembly requirement is adopted for the ultra-fine pitch interconnects. A process for manufacturing 20- μm pitch compliant-bumps is proposed for ACA-bonded COF packages. The double-layer ACA consists of an ACA layer with a diameter of 2.8 μm conductive particles and an NCA layer as an interlayer to bind a silicon chip with a flexible substrate. The bonding accuracy for ultra-fine pitch is determined using X-rays. To evaluate the quality of bonding, the electrical insulation is tested and the contact resistance of the daisy chain with 606 input/output (I/O) around the periphery of the chip is measured. The double-layer ACA material is assembled at different bonding temperatures to study the effects of bonding temperature on the interface adhesion using differential scanning calorimetry (DSC) and a 90° peeling test. The reliability of the fabricated COF interconnects is also evaluated by performing an 85°C/85% relative humidity thermal humidity storage test (RH THST) for 1000 h and a -55°C ~ 125°C thermal cycling test (TCT) for 1000 cycles. The interfaces between the silicon chip and the substrate of the failed samples in the reliability tests are then observed using the cross-sectional scanning electron microscopy (SEM). The compliant-bump-bonded samples with the double-layer ACA provide their excellent electrical insulation performance even at a joint space of 5 μm whereas the Au-bump samples have a short-circuiting rate of more than 50%. Notably, the contact resistance also remains stable and varies by under 3% in both the RH THST for 1000 h and the TCT for 1000 cycles. The presented results show the reliable bonding quality and stable contact resistance of the COF package that is bonded with the compliant-bump structure using the double-layer ACA, indicating its great potential for use in ultra-fine pitch applications.

Simulation study on the influences of the bonding parameters on the warpage of chip-on-glass module with nonconductive film

Nonconductive film (NCF) interconnection technology is now being used for the ultrafine pitch interconnections in chip-on-glass (COG) packaging. In comparison to traditional anisotropic conductive film (ACF) technology, NCF can reach less than 10μm ultrafine pitch interconnection, while ACF just reaches the limit of 30μm. For NCF interconnection technology used in COG bonding, it needs a higher bonding pressure and temperature than those in ACF bonding, so the warpage is very important for the reliability of the package. In this paper, an exploring study investigated the effects of the structure design and bonding process on the warpage in a COG module. The warpage increased linearly with the increase in bonding head temperature and bonding force, but it decreased with the increase in substrate temperature, substrate thickness, and chip thickness. The large temperature difference between the substrate and chip produced a high thermal stress, and the large bonding force generated a high mechanical stress. The thermal and mechanical stresses were the reasons for warpage in a COG module. For the high reliability, the design and bonding process to the COG module with NCF should adopt a thick substrate, an appropriate bonding force, and a low temperature difference.

Review of Recent Advances in Electrically Conductive Adhesive Materials and Technologies in Electronic Packaging

Electrically Conductive Adhesives (ICAs: Isotropic Conductive Adhesives; ACAs: An-isotropic Conductive Adhesives; and NCAs: Non-conductive Adhesives) offer promising material solutions for fine pitch interconnects, low cost, low-temperature process and environmentally clean approaches in the electronic packaging technology. ICAs have been developed and used widely for traditional solder replacement, especially in surface mount devices and flip chip application. These also need to be lower cost with higher electrical/mechanical and reliability performances. ACAs have been widely used in flat panel display modules for high resolution, lightweight, thin profile and low power consumption in film forms (Anisotropic Conductive Films: ACFs) for last decades. Multi-layered ACF structures such as double and triple-layered ACFs were developed to meet fine pitch interconnection, low-temperature curing and strong adhesion requirements. Also, ACAs have been attracting much attention for their simple and lead-free processing as well as cost-effective packaging method for semiconductor packaging applications. High mechanical reliability, good electrical performance at high frequency level and effective thermal conductivity for high current density are some of required properties for ACF materials to be pursued for a wide usage in flip chip technology. Recently, NCAs are becoming promising for ultra-fine pitch interconnection and low cost joining materials in electronic packaging applications. In this paper, an overview of the recent developments and applications of electrically conductive adhesives for electronic packaging with focus on fine pitch capability, electrical/mechanical/thermal performance and wafer level packaging application is presented.

Research on the contact resistance, reliability, and degradation mechanisms of anisotropically conductive film interconnection for flip-chip-on-flex applications

Although there have been many years of development, the degradation of the electrical performance of anisotropically conductive adhesive or film (ACA or ACF) interconnection for flip-chip assembly is still a critical drawback despite wide application. In-depth study about the reliability and degradation mechanism of ACF interconnection is necessary. In this paper, the initial contact resistance, electrical performance after reliability tests, and degradation mechanisms of ACF interconnection for flip-chip-on-flex (FCOF) assembly were studied using very-low-height Ni and Au-coated Ni-bumped chips. The combination of ACF and very-low-height bumped chips was considered because it has potential for very low cost and ultrafine pitch interconnection. Contact resistance changes were monitored during reliability tests, such as high humidity and temperature and thermal cycling. The high, initial contact resistance resulted from a thin oxide layer on the surface of the bumps. The reliability results showed that the degradation of electrical performance was mainly related to the oxide formation on the surface of deformed particles with non-noble metal coating, the severe metal oxidation on the conductive surface of bumps, and coefficient of thermal expansion (CTE) mismatch between the ACF adhesive and the contact conductive-surface metallization. Some methods for reducing initial contact resistance and improving ACF interconnection reliability were suggested. The suggestions include the removal of the oxide layer and an increase of the Au-coating film to improve conductive-surface quality, appropriate choice of conductive particle, and further development of better polymeric adhesives with low CTE and high electrical performance.