Ultra Fine Pitch Flip Chip Research Articles

Fatigue Testing of Copper Nanoparticle-Based Joints and Bonds

Abstract Fused or sintered Cu nanoparticle structures are potential alternatives to solder for ultrafine pitch flip chip assembly and to sintered Ag for heat sink attach in high-temperature micro-electronics. Meaningful testing and interpretation of test results in terms of what to expect under realistic use conditions do, however, require a mechanistic picture of degradation and damage mechanisms. As far as fatigue goes, such a picture is starting to emerge. The porosity of sintered nanoparticle structures significantly affects their behavior in cycling. The very different sensitivities to parameters, compared to solder, mean new protocols will be required for the assessment of reliability. This study focused on fatigue in both isothermal and thermal cycling. During the latter, all damage occurs at the low-temperature extreme, so life is particularly sensitive to the minimum temperature and any dwell there. Variations in the maximum temperature up to 125 °C did not affect, but a maximum temperature of 200 °C led to much faster damage. Depending on particle size and sintering conditions, deformation and damage properties may also degrade rapidly over time. Our picture allows for recommendations as to more relevant test protocols for vibration, thermal cycling, and combinations of these, including effects of aging, as well as for generalization of test results and comparisons in terms of anticipated behavior under realistic long-term use conditions. Also, the fatigue life seems to vary with the ultimate strength, meaning that simple strength testing becomes a convenient reference in materials and process optimization.

High Productivity Thermo-Compression Flip Chip Bonding

Advancements in electronic packaging performance and cost have historically been driven by higher integration primarily provided by fab shrinks that has followed the well-known Moore's law. However, due to the tremendous and continuously increasing cost of building new fabs, the performance/cost improvements achieved via node shrinks are negated. This leaves packaging innovation as the vehicle to achieve future cost-performance improvements. This has initiated a More-than-Moore idea that has led to vigorous R&D in packaging. Advanced packages which employ ultra-fine pitch flip chip technology for chip-to-substrate, chip-to-chip, or chip-to-interposer for the first level interconnect have been developed as an answer to obtaining higher performance. However, the costs are too high as compared to traditional wire bonding. The status today is that the fundamental technical hurdles of manufacturing the new advanced packages have been solved, but cost reduction and yield improvements have to be addressed for large-scale adoption into high volume manufacturing. In traditional flip chip assembly silicon chips are tacked onto a substrate and then the solder joints are melted and mass reflowed in an oven. This mass reflow technique is troublesome as the pitch of the solder bumps become finer. This is due to the large differences in the thermal expansion coefficient of the die and the substrate, which creates stress at the solder joints and warpage of the package when the die and substrate are heated and cooled together. To mitigate and resolve this issue, thermo-compression bonders have been developed which locally reflow the solder without subjecting the entire substrate to the heating and cooling cycle. This requires that the bondhead undergo heating past the melting point of solder and then cooling down to a low enough temperature to pick the next die from the wafer that is mounted to tape. Machines in the market today can accomplish this temperature cycle in 7 to 15 seconds. This is substantially slower than the standard flip chip process which leads to high cost and is delaying the introduction of these new packages. This paper shows a flip chip bonder with a new heating and cooling concept that will radically improve the productivity of thermo-compression bonding. Data and productivity cycles from this new bond head with heating rates of over 200°C/sec and cooling of faster than 100°C/sec are revealed. Experimental results are shown of exceptional temperature accuracy across the die of 5°C throughout the cycle and better than 3°C at the final heating stage. The high speed thermo-compression bonds are analyzed and the efficacy of the new concept is proven. Excellent temperature uniformity while heating rapidly is an absolute necessity for enabling good solder joints in a fast process. Without good temperature uniformity, additional dwell times need to be incorporated to allow heat to flow to all of the joints, negating any benefits from rapid heating. Whereas the current state-of-that-art is often to program temperature in steps, this bonder can be commanded and accurately follows more complex temperature profiles with great accuracy. Examples of how this profiling can be used to enhance the uniformity and integrity of the joints with non-conductive pastes, film, and without underfill along with the associated productivity improvements will be shown. Tests that show portability across platforms that will lead to set up time and yield improvements and are identified and quantified. Additionally new ideas for materials and equipment development to further enhance productivity and yield are explored.

Particle on Bump (POB) technique for ultra-fine pitch chip on glass (COG) applications by conductive particles and adhesives

Chip on glass (COG) technology is widely used in liquid crystal display (LCD) modules for connecting driver ICs to the displays especially for middle and small size panels. The most common COG technology currently used in display applications is based on anisotropic conductive films (ACF). As the increasing demand in higher resolution and cost reduction, the bump pitch of the driver ICs becomes finer and finer. With the reduction of bump pitch, the current ACF based COG technology is confronted with two issues: one is the increase of the chances of open circuit; the other is the increase of the chances of forming shorts. A new approach for ultra-fine pitch chip on glass (COG) bonding, named ”Particle on Bump (POB)”, is proposed in this paper. In this technique, conductive particles are planted on the top surface of bumps of a driver IC through Au–Sn intermetallic connection. The driver IC is then assembled on the glass substrate of a LCD panel with an insulated adhesive by thermal press. The new method ensures that electrical connections are established only between bumps and corresponding pads. The Au–Sn reflow process for particle planting and corresponding COG bonding process were investigated in detail. The results showed that reliable connections were formed between particles and bumps through an Au–Sn intermetallic layer and final COG interconnections thus formed performed well in reliability tests. It is concluded that the POB technique overcomes the shortcomings of current ACF technique and has good potential to provide a viable ultra-fine pitch flip chip on glass solution for display applications.

Effect of preformed IMC Layer on Electromigration of Solder Capped Cu Pillar Bump Interconnection on an organic substrate

The electromigration behavior of 80 μm pitch solder capped Cu pillar bump interconnection on an organic carrier is studied and discussed. Recently the solder capped Cu pillar bump technology has been widely used in mobile applications as a peripheral ultra fine pitch flip chip interconnection technique. The solder capped Cu pillar bumps are formed on Al pads which are commonly used in wirebonding technique. It allows us an easy control of the space between the die and the substrate simply by varying the Cu pillar height. Since the control of the collapse of the solder bumps is not necessary, the technology is called the “C2 (Chip Connection)”. Solder capped Cu pillar bumps are connected to OSP surface treated Cu substrate pads on an organic substrate by reflow with a no-clean process, hence the C2 is a low cost ultra fine pitch flip chip interconnection technology. It is an ideal technology for the systems requiring fine pitch structures. In 2011, the EM tests were performed on 80 μm pitch solder capped Cu pillar bump interconnections and the effects of Ni barrier layers on the Cu pillars and the preformed intermetallic compound (IMC) layers on the EM tests were studied. The EM test conditions of the test vehicles were 7–10 kA/cm2 at 125–170°C. The Cu pillar height was 45 μm and the solder height was 25 μm. The solder composition was Sn-2.5Ag. Aged condition for pre-formed IMCs was 2,000 hours at 150°C. It was shown that the formation of the pre-formed IMC layers and the insertion of Ni barrier layers are effective in reducing the Cu atoms dissolution. In this report, it is studied that which of the IMC layers, Cu3Sn or Cu6Sn5, is more effective in preventing the Cu atom dissolution. The cross-sectional analyses of the joints after the 2000 hours of the test with 7kA/cm2 at 170°C were performed for this purpose. The relationship between the thickness of Cu3Sn IMC layer and the Cu migration is also studied by performing the current stress tests on the joints with controlled Cu3Sn IMC thicknesses. The samples were thermally aged prior to the tests at a higher temperature (200°C) and in a shorter time (10–50 hours) than the previous experiments. The cross-sectional analyses of the Sn-2.5Ag joints without pre-aging consisting mostly of Cu6Sn5, showed a significant Cu dissolution while the Cu dissolution was not detected for the pre-aged joints with thick Cu3Sn layers. A large number of Kirkendall voids were also observed in the joints without pre-aging. The current stress tests on the controlled Cu3Sn joints showed that Cu3Sn layer thickness of more than 1.5 μm is effective in reducing Cu dissolution in the joints.

Microstructure Observation of Electromigration Behavior in Peripheral C2 Flip Chip Interconnection with Solder Capped Cu Pillar Bump

The electromigration behavior of 80μm bump pitch C2 (Chip Connection) interconnection is studied and discussed. C2 is a peripheral ultra fine pitch flip chip interconnection technique with solder capped Cu pillar bumps formed on Al pads that are commonly used in wirebonding technique. It allows us an easy control of the space between dies and substrates simply by varying the Cu pillar height. Since the control of the collapse of the solder bumps is not necessary, the technology is called the “C2 (Chip Connection)”. C2 bumps are connected to OSP surface treated Cu substrate pads on an organic substrate by reflow with no-clean process, hence the C2 is a low cost ultra fine pitch flip chip interconnection technology. The reliability tests on the C2 interconnection including thermal cycle tests and thermal humidity bias tests have been performed previously. However the reliability against electromigration for such small flip chip interconnections is yet more to investigate. The electromigration tests were performed on 80μm bump pitch C2 flip chip interconnections. The interconnections with two different solder materials were tested: Sn-2.5Ag and Sn100%. The effect of Ni layers electroplated onto the Cu pillar bumps on electromigration phenomena is also studied. From the cross-sectional analyses of the C2 joints after the tests, it was found that the presence of intermetallic compound (IMC) layers reduces the atomic migration of Cu atoms into Sn solder. The analyses also showed that the Ni layers are effective in reducing the migration of Cu atoms into solder. In the C2 joints, the under bump metals (UBMs) are formed by sputtered Ti/Cu layers. The electro-plated Cu pillar height is 45μm and the solder height is 25μm for 80μm bump pitch. The die size is 7.3-mm-square and the organic substrate is 20-mm-square with a 4 layer-laminated prepreg with thickness of 310μm. The electromigration test conditions ranged from 7 to 10 kA/cm2 with temperature ranging from 125 to 170°C. Intermetallic compounds (IMCs) were formed prior to the test by aging process of 2,000hours at 150°C. We have studied the effect of IMC layers on electromigration induced phenomena in C2 flip chip interconnections on organic substrates. The study showed that the IMC layers in the C2 joints formed by aging process can act as barrier layers to prevent Cu atoms from diffusing into Sn solder. Our results showed potential for achieving electromigration resistant joints by IMC layer formation. The FEM simulation results show that the current densities in the Cu pillar and the solder decrease with increasing Cu pillar height. However an increase in Cu pillar height also leads to an increase in low-k stress. It is important to design the Cu pillar structure considering both the electromigration performance and the low-k stress reduction.

Technical challenges of stencil printing technology for ultra fine pitch flip chip bumping

Stencil printing remains the technology route of choice for flip chip bumping because of its economical advantages over traditionally costly evaporation and electroplating processes. This paper provides the first research results on stencil printing of 80 and 60 μm pitch peripheral array configurations with Type 7 Sn63/Pb37 solder paste. In specific, the paste particle size ranges from 2 to 11μm with an average particle size of 6.5 μm taken into account for aperture packing considerations. Furthermore, the present study unveils the determining role of stencil design and paste characteristics on the final bumping results. The limitations of stencil design are discussed and guidelines for printing improvement are given. Printing of Type 7 solder paste has yielded promising results. Solder bump deposits of 25 and 42 μm have been demonstrated on 80 μm pitch rectangular and round pads, respectively. Stencil printing challenges at 60 μm pitch peripheral arrays are also discussed.

Low cost bumping by stencil printing: process qualification for 200 μm pitch

Area array packages (flip chip, CSP (Chip scale packages) and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment and/or are limited by the throughput, minimal pitch and yield, the industry is currently searching for new and lower cost bumping approaches. The experimental work of stencil printing to create solder bumps for flip chip devices is described in detail in this article. In the first part of this article, a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented, and the limits concerning pitch, stencil design, reproducibility and bump height will be discussed in detail. In the second part, a comparison of measured standard deviations of bump heights as well as the quality demands for ultrafine pitch flip chip assembly are shown.