Types Of Thin-film Transistors Research Articles

Hybrid Nanostructures Based of Ta2O5-PMMA for Electronic Applications

The scientific interest on hybrid materials is mainly related to understanding the types of interactions between inorganic and organic component and the effect of these interactions on the properties of the new material formed. Hybrid nanostructured materials and especially dielectrics are used for electronics (for gate layer) and especially those applicable in structure of different types of thin film transistors (TFTs).In this paper is presented the research on thin film hybrid materials based on tantalum oxide (Ta2O5) starting with inorganic precursor - tantalum ethoxide and polymethylmethacrylate (PMMA). The chemical method sol -gel involves the precursor-tantalum ethoxide which is hydrolysed and functionalized (with special siloxane compound), and the organic methyl methacrylate monomer. The chemical reactions take place at low temperature below 160 oC. The sol is deposited as thin films by spin-coating to analyse intensity-voltage (I-V) and capacitance-voltage curves (C-V) to determine the electric properties. Metal-Insulator-Metal (MIM) structures were made-up for electric characterisation. The value of leakage currents was between 10-10 - 10-7 A at ± 40 V. The hybrid films were analysed by scanning electron microscopy (SEM) for thickness and morphology and for thermal stability the sol was investigated by TG and DSC.The dielectric permittivity ranges between 3.5 and 4 at 1 MHz, depending on the tantalum alkoxide: MMA molar ratio, showing good behaviour for gate layer in future TFTs.

A Light Shield Temperature Sensor for a Display Backplane

Liquid Crystal Display (LCD) and Organic Light Emitting Diode (OLED) display are operated by voltage or current driving. Several types of Thin-Film Transistor (TFT) are used in the backplane of a display, LTPS and a-IGZO TFTs are those. As the applied voltage increases to increase the brightness of the display, heat generation also increases at the channel of the TFT. Such heat generation increase the temperature, which degrades the characteristics of the TFT, and decrease the lifetime of the organic device. Therefore, in order to keep the quality of the display, it is necessary to monitor the temperature of the display and control related signals to implement optimal image quality. There are various temperature sensors which can be used to detect such a temperature change in a display. In the case of using a discrete temperature sensor, the process and cost are increased by attaching the temperature sensor additionally. However, in the case of a temperature sensor integrated into the display, an process for the temperature sensor is not necessary. One way to integrate is using resistance changing material with a reference resistor outside. In this case, temperature accuracy can be reduced when the reference resistance changes due to the influence of the external temperature. To solve the problem, external reference resistance is removed in this proposed sensor scheme. Figure 1 shows the developed thin-film temperature sensor, which consists of two wires connected in series. The temperature coefficients of Molybdenum (Mo) and Indium Tin Oxide (ITO) are different from each other, and that of ITO is about 1.2 times or more than that of Mo. In this scheme, no external resistance is required. In addition, to reduce the process steps, a thin film temperature sensor is designed to replace a light shield layer which is formed at the bottom of the active layer to prevent the input of light. The two thin film materials are connected in series and the voltages at a connecting point are measured. The generated heat transferred to the temperature sensor was tested for repeatability and accuracy. The thin-film temperature sensor was designed to be located at the bottom of a-IGZO Top Gate TFT structure to check the heating during the operation of TFT. an interlayer insulation film was deposited on the temperature sensor before deposition of the active layer. The temperature of the TFT was measured by a temperature sensor Figure 1. shows the schematic cross-sectional structure of the developed oxide TFT with an integrated temperature sensor. Figure 1

(Invited, Digital Presentation) Evaluation of Polycrystalline-Si1-XGex Thin-Film Transistors Grown Laterally on a Glass Substrate Using a Continuous-Wave Laser

System-on-glass requires high-performance thin-film transistors (TFTs). In order to realize high-performance polycrystalline-Si (poly-Si) TFTs, we grew high-quality poly-Si thin films using a continuous-wave solid-state laser, in a method known as continuous-wave laser lateral crystallization (CLC). The grain boundary (G.B.) of CLC poly-Si is characterized by being parallel to the laser scan direction with shape of nearly straight line. Ge-based devices are attractive because of the superior carrier mobility of Ge in comparison to Si; however, as carriers in poly-Ge thin film are high concentration of hole generated from defects, it is difficult to control the level of doping. Moreover, fabrication of stable gate dielectric GeO2 is highly challenging. Addition of Ge to Si is expected to improve carrier mobility in Si, leading to poly-Si1-xGex TFTs with better performance than conventional poly-Si TFTs. Hence, our work here is a step in that direction. The purpose of this study is to understand the performance of poly-Si1-xGex TFTs, and to highlight the issues pertaining to poly-Si1-xGex thin films by comparing the performance of poly-Si1-xGex TFTs with that of poly-Si TFTs.A typical TFT fabrication process is as follows. An amorphous Si1-xGex thin film (~100 nm) with a Ge concentration of 10% is grown on a quartz substrate. After cleaning the substrate surface with hydrogen fluoride solution, CLC is carried out in air without substrate heating, followed by the preparation of transistor islands using reactive ion etching (RIE). A 50-nm-thick SiO₂ film is deposited by plasma enhanced chemical vapor deposition (PECVD), followed by heat treatment in nitrogen atmosphere at 550 °C for 4 h and deposition of Mo film as the top gate. Next, P or BF₂ is ion-implanted into poly-Si1-xGex for source-drain (SD) respectively, at 10 keV and 3×1015 cm-2. After ion implantation is completed, interlayer dielectric SiO2 film is deposited by PECVD and activated by heating in nitrogen atmosphere at 550 °C for 6 h. Subsequently, contact holes and Mo electrodes are formed. Finally, hydrogenation using step-cooling is performed to complete the TFT. N-channel (n-ch) and P-channel (p-ch) poly-Si TFTs are also fabricated using identical processes. Two types of TFTs were fabricated for both poly-Si1-xGex TFTs and poly-Si TFTs: one with the G.B. lying parallel to the SD direction (parallel type) and the other with the G.B. perpendicular to the SD direction (perpendicular type).The transfer characteristics of n-ch TFTs showed that the threshold voltages (Vth) of poly-Si1-xGex shifted in the positive direction in comparison with those of poly-Si TFTs. The mobility and sub-threshold swing (s.s.) values of poly-Si1-xGex were inferior to those of poly-Si TFTs, for both the parallel and perpendicular types.Considering the p-ch TFTs, the transfer characteristics of parallel poly-Si1-xGex TFTs showed higher OFF current and lower ON current than the corresponding poly-Si TFTs. In case of perpendicular types, OFF currents of poly-Si1-xGex TFTs were comparable with that of poly-Si TFTs and ON currents of poly-Si1-xGex TFTs were lower than those of poly-Si TFTs. Moreover, Vth values of poly-Si1-xGex TFTs were shifted in the positive direction in comparison to those of poly-Si TFTs, for both parallel and perpendicular types.The segregation coefficient of Ge in Si is less than 1.0, and it has been shown that Ge segregates to G.B.s in poly-Si1-xGex thin films during solidification. As acceptors are generated in regions with high Ge concentration along G.B.s, p-type quasi-one-dimensional conduction regions were formed in Si1-xGex along G.B.s. Therefore, when SD regions are parallel to a G.B., a current path connecting those regions is formed along G.B.s in p-type poly-Si1-xGex TFTs, leading to enhancement of OFF current. However, when G.B.s lie perpendicular to SD regions, the latter remain unconnected, leading to normal OFF current values.The positive shift in Vth of poly-Si1-xGex TFTs can be explained by the formation of acceptors. It can also be concluded that the decrease of ON current in poly-Si1-xGex TFTs is due to ionized impurity scattering by the acceptors. In addition, the difference in the magnitude of ON current depending on the G.B. direction can be explained as follows: when G.B.s are parallel to the SD direction, ON current is higher than that of the perpendicular type, because G.B.s do not act as strong scattering centers.In summary, the characteristics of CLC poly-Si1-xGex TFTs can be explained by the formation of acceptors. In particular, the large OFF current in parallel p-ch poly-Si1-xGex TFTs is explained by Ge segregation along G.B.s, resulting in formation of quasi-one-dimensional p-type conduction channels and electrical connection between SD region.

Bottom-up water-based solution synthesis for a large MoS2 atomic layer for thin-film transistor applications

A bottom-up water-based solution-process method was developed for atomic layered MoS2 with a one-step annealing process and no sulfurization. The chosen MoS2 precursor is water soluble and was carefully formulated to obtain good coating properties on a silicon substrate. The coated precursor was annealed in a furnace one time to crystallize it. This method can obtain a large and uniform atomic layer of 2D MoS2 with 2H lattice structure. The number of atomic layers (4–7) was controlled through the precursor concentrations and showed good uniformity, which was confirmed by STEM and AFM. Four types of thin-film transistors (TFTs) were prepared from the solution-processed MoS2 on Al2O3 and SiO2 dielectric with either thermal evaporated Al or printed Ag source and drain electrodes. The best result shows an improved mobility of 8.5 cm2 V−1 s−1 and a reasonable on–off ratio of about 1.0 × 105 with solid output saturation.

Complementary Inverter Circuits Based on p-Cu2O and n-ZTO Thin Film Transistors

This paper describes the fabrication of copper oxide and zinc tin oxide complementary inverters where both the p-type and n-type channels were deposited by RF magnetron sputtering. We have designed low-voltage and high gain complementary inverters by combining a set of p channel copper oxide and n channel zinc tin oxide thin film transistors (TFTs) with different aspect ratios, thus reducing the difference in mobility and threshold voltage between both types of TFTs. The complementary inverters with four different geometric aspect ratios were fabricated using top-contact configuration. The voltage gain increase with aspect ratio and a maximum value of 4.2 was reached for an aspect ratio of 2 (Wp:Wn = 7200 μm/3600 μm). The voltage gain was found to be dependent on the SS value of p-type TFTs. It is also noticed that an inverter having a geometric aspect ratio of 2 gave better voltage gain and noise margin values. For a VDD = 20 V the NMH and NML values are 7 V and 6.5 V, respectively.

Grayscale Image Recognition Using Spike-Rate-Based Online Learning and Threshold Adjustment of Neurons in a Thin-Film Transistor-Type NOR Flash Memory Array.

As a synaptic device, TFT-type NOR flash memory cell shows reasonable weight levels (50 levels for long-term potentiation (LTP) and 150 levels for long-term depression (LTD)) and large max/min ratio (═50) for synapse weight. Based on the measurement results of the synapse cell, supervised learning process is simulated using software MATLAB. A new pulse scheme is designed for mimicking spike-rate-dependent plasticity (SRDP) algorithm. Through learning and inferencing phase, our (784 × 100) network achieved 74.08% accuracy on the MNIST benchmark. A new method for adapting the threshold voltage of output neurons for firing is also proposed. This additional adjustment helps to eliminate the exclusive or dormant output neurons by setting the threshold voltage to an appropriate value proportional to the average weight of synapses connected to each neuron. As a result, accuracy increases to 82.54% in the (784 × 100) network and to 84.14% in the (784 × 200) network. Moreover, threshold adjustment helped the network to classify completely overlapped patterns in succession.

Mechanical stress-induced degradation model of amorphous InGaZnO thin film transistors by strain-initiated defect generation

For the applications of next generation display, various types of thin-film transistors (TFTs) are actively researched. Among them, the indium‑gallium‑zinc-oxide (IGZO) TFTs are being focused because of its transparency and other great electrical properties. However, the effect of mechanical stress on amorphous IGZO (a-IGZO) TFTs has to be studied for the foldable display application. In this paper, we examine the reliability of mechanical stress on a-IGZO TFTs and report the degradation mechanism by analyzing sub-gap density of states (DOSs) extracted from the stress simulation model. The simulation model has been implemented through TCAD simulation tool and the electrical characteristics based on the extracted parameters are compared with the measured data.

The effect of ITO and Mo electrodes on the properties and stability of In-Ga-Zn-O thin film transistors

The effect of ITO and Mo electrodes on the electrical properties and stability of In-Ga-Zn-O (IGZO) thin film transistors (TFTs) are investigated. While the field effect mobility values of the devices employing ITO and Mo electrodes are similar, the former exhibit smaller threshold voltage (Vth) and subthreshold swing (SS). It is suggested that the relatively large workfunction of Mo (4.7 eV) compared to that of ITO (4.4 ~ 4.5 eV) induces a large Schottky barrier at the Mo/IGZO junction, which prohibits the effective injection of electrons from the metal into the IGZO semiconductor. The workfunction of IGZO is usually reported to be approximately 4.5 eV. The device stability of the two types of TFTs under negative bias stress (NBS) and positive bias stress (PBS) is similar, which implies that the degradation of the devices under bias stress is mainly affected by the trapping of carriers at the IGZO/gate insulator interface. In the presence of illumination, the devices using optically transparent ITO electrodes allow the penetration of a more abundant concentration of photons into the IGZO active layer, and thus undergo larger Vth shifts under negative bias illumination stress (NBIS). However, under positive bias illumination stress (PBIS), the TFTs using ITO exhibit smaller positive Vth shifts. The latter phenomenon is suggested to result from the excess photo-induced electrons in the bulk that counter the effect of electron trapping near the IGZO/gate insulator boundary.

An effective powerful test for one-sided supplier selection problem with multiple independent characteristics

In this paper, we use the index to investigate the supplier selection problem for one-sided processes with multiple independent characteristics. We first review the existing approach, which we refer to as the division method, then develop a new exact approach called the subtraction method. A two-stage selection procedure is developed based on the subtraction method for practical applications. We then compared the two methods with regard to selection power. The results show that the subtraction method we propose is indeed more powerful than the existing division method. A thin-film transistor type liquid-crystal display (TFT-LCD) application example is provided to illustrate the testing procedure.

High voltage surface potential measurements in ambient conditions: Application to organic thin-film transistor injection and transport characterization

A scanning surface potential measurement technique suited for thin-film devices operating under high voltages is reported. A commercial atomic force microscope has been customized to enable a feedback-controlled and secure surface potential measurement based on phase-shift detection under ambient conditions. Measurements of the local potential profile along the channel of bottom-gate organic thin-film transistors (TFTs) are shown to be useful to disentangle the contributions from the channel and contacts to the device performance. Intrinsic contact current-voltage characteristics have been measured on bottom-gate, top-contact (staggered) TFTs based on the small-molecule semiconductor dinaphtho[2,3-b:2′,3-f]thieno[3,2-b]thiophene (DNTT) and on bottom-gate, bottom-contact (coplanar) TFTs based on the semiconducting polymer polytriarylamine (PTAA). Injection has been found to be linear in the staggered DNTT TFTs and nonlinear in the coplanar PTAA TFTs. In both types of TFT, the injection efficiency has been found to improve with increasing gate bias in the accumulation regime. Contact resistances as low as 130 Ω cm have been measured in the DNTT TFTs. A method that eliminates the influence of bias-stress-induced threshold-voltage shifts when measuring the local charge-carrier mobility in the channel is also introduced, and intrinsic channel mobilities of 1.5 cm2 V−1 s−1 and 1.1 × 10−3 cm2 V−1 s−1 have been determined for DNTT and PTAA. In both semiconductors, the mobility has been found to be constant with respect to the gate bias. Despite its simplicity, the Kelvin probe force microscopy method reported here provides robust and accurate surface potential measurements on thin-film devices under operation and thus paves the way towards more extensive studies of particular interest in emerging fields of solid-state electronics.

Performance Evaluation of Thin Film Transistors: History, Technology Development and Comparison: A Review

In the past several years, the thin film transistor technology has progressed intensely, especially in the low temperature, large-area, high throughput fabrication process. Recently, various thin film transistors (TFT) technological sources have been realized, indicating that new information appliances that match new information infrastructures and lifestyles will be available in the future. In this paper, we review different types of TFTs, including amorphous silicon, polysilicon, organic and oxide TFTs. We report here on different techniques e.g. fabrication and simulation based which has been developed to accurately simulate TFT characteristics and to improve the understanding of the device operation. Here, we highlight the problem gap in the TFT technology that includes downscaling of TFTs and stability of p-type zinc oxide (ZnO) TFTs and ways to improve it.

A low‐cost low‐temperature thin‐film‐transistor backplane based on oxide semiconductor

Abstract— An indium‐gallium‐zinc‐oxide (IGZO) thin‐film transistor (TFT) based on an anodized aluminum‐oxide gate dielectric and photoresist passivation has been fabricated. The TFT showed a field‐effect mobility of as high as 18 cm2/V‐sec and a threshold voltage of only 0.5 V. A 50 × 50 AMOLED display based on this type of TFT was designed and fabricated. The average luminance of the panel was 150 cd/m2, and the maximum pixel luminance was 900 cd/m2.

(Invited) Single-Grain Germanium TFTs

We review our recent achievements in location-control of Ge grains and high performance single-grain (SG) Ge thin film transistor (TFT) fabricated inside a Ge grain. Large Ge grains having a grain size of 10 µm were obtained at predetermined positions by the µ-Czochralski process using excimer-laser and sputtered a-Ge layer. TFTs were fabricated inside the single grain of Ge. Capping silicon dioxide was applied before the laser crystallization with which a high quality Ge/insulator interface was formed during the laser annealing. Source/drain regions were formed by doped Si instead of the Ge, which ensures a low contact resistance and suppresses fast dopant diffusion in the channel. N- and p-channel SG Ge TFTs showed electron and hole mobility of as high as 3337cm^2/Vs and 1719cm^2/Vs, respectively. On/off current ratio for the both types of TFTs was in the order of 10^7.

Effect of fluorination and hydrogenation by ion implantation on reliability of poly-Si TFTs under gamma irradiation

Sputtered thin film transistors (TFTs), which were hydrogenated and fluorinated by ion implantation, were exposed to gamma irradiation up to 2500 Gy. Long term post-irradiation stability of TFTs was studied after eight months of storage and under positive bias test at 150 °C in time intervals of 1–10 h. The effects induced by irradiation and during relaxation period were monitored by current–voltage (I–V) measurements. I–V data were used to determine post-irradiation changes in different TFT parameters, such as threshold voltage, interface states density and grain boundaries trap density. The behaviour of these parameters was compared for four types of TFTs: non-fluorinated-hydrogenated, fluorinated, hydrogenated and fluorinated-hydrogenated, and it was found that hydrogenated TFTs showed greater instability. A mechanism for grain boundary traps generation is proposed.

Thin‐film transistors fabricated from semiconductor‐enriched single‐wall carbon nanotubes

AbstractSolution‐processed thin‐film transistors (TFTs) were fabricated from semiconductor‐enriched single‐wall carbon nanotubes (SWCNTs). By coating with a self‐assembled monolayer of aminosilanes, one drop of SWCNT solution produced a uniform SWCNT random network on a SiO2/Si substrate. Thin films prepared by this method were used to fabricate SWCNT‐TFTs and high‐yield fabrication and stable transfer characteristics were achieved. We prepared three types of TFTs from pristine, metal‐enriched, and semiconductor‐enriched SWCNTs. All TFTs fabricated from semiconductor‐enriched SWCNTs exhibited on/off ratios greater than 104, whereas the other TFTs had much lower on/off ratios. This result clearly demonstrates the advantage of using semiconductor‐enriched SWCNTs for device applications and is expected to lead to integrated circuits made from SWCNTs in the near future.

Carbon nanotube thin film transistors based on aerosol methods

We demonstrate a fabrication method for high-performance field-effect transistors(FETs) based on dry-processed random single-walled carbon nanotube networks(CNTNs) deposited at room temperature. This method is an advantageous alternativeto solution-processed and direct CVD grown CNTN FETs, which allows usingvarious substrate materials, including heat-intolerant plastic substrates, and enablesan efficient, density-controlled, scalable deposition of as-produced single-walledCNTNs on the substrate directly from the aerosol (floating catalyst) synthesisreactor. Two types of thin film transistor (TFT) structures were fabricated toevaluate the FET performance of dry-processed CNTNs: bottom-gate transistors onSi/SiO2 substrates and top-gate transistors on polymer substrates. Devices exhibited on/off ratios up to105 and field-effectmobilities up to 4 cm2 V−1 s−1. The suppression of hysteresis in the bottom-gate device transfer characteristics by meansof thermal treatment in vacuum and passivation by an atomic layer depositedAl2O3 film was investigated.A 32 nm thick Al2O3 layer was found to be able to eliminate the hysteresis.

Universal compact model for long- and short-channel Thin-Film Transistors

We present a compact modelling scheme valid for the different types of Thin-Film Transistors (TFTs) including a-Si, poly-Si, ZnO, and organic TFTs. This modelling is based on the use eight-parameter universal model, valid for all types of TFTs, which allows easy extraction. This universal basic TFT model is used as a first iteration in complete models adapted to each type of TFTs, in order to calculate the intrinsic voltage bias and the rest of parameters, which depend on the channel current or on the bias. A contact transistor is added between the source and the intrinsic device in order to model the nonlinear contact effects (from the source contact into the film), which may affect the I– V characteristics of short-channel devices. Good agreement has been found with experimental measurements of long and short-channel TFTs.

Microcrystalline silicon and excimer laser crystallized silicon Thin Film Transistors on the same substratel

Integration of microcrystalline silicon Thin Film Transistors (TFTs) and excimer laser crystallized silicon TFTs on the same substrate is performed with the objective to limit the maximum temperature of the process to 200 °C. For the second type of TFTs, the laser crystallization of 200 nm thick microcrystalline silicon deposited film was optimised first. The maximum electron mobility of both μc-Si and laser crystallized TFTs is 4 cm 2/V s and 400 cm 2/V s respectively.

Comparative studies on the stability of polymer versus SiO2 gate dielectrics for pentacene thin-film transistors

The authors report on the electrical reliabilities of poly-4-vinyl phenol (PVP) and SiO2 gate dielectrics for pentacene thin-film transistors (TFTs). SiO2 films were grown by dry oxidation and PVP films were prepared by spin coating and subsequent cross-linking at 175°C for 15min. The pentacene TFTs with the PVP cured for 15min exhibited a large hysteresis and an abnormal drain-current increase under a gate bias stress over time, while the other TFT with SiO2 displayed a small hysteresis but its drain current decreases with time. The hysteresis behaviors induced by PVP and SiO2 were opposite to each other in the gate bias swing direction, due to the difference in hysteresis mechanism between the two types of TFTs. Comparing their hysteresis behavior, the authors fabricated a far more reliable pentacene TFT with PVP by extending the PVP curing time to 1h. Our improved device with PVP exhibited no hysteresis and persistent toughness to the gate bias stress.

Evaluation of Electrical Characteristics and Trap-State Density in Bottom-Gate Polycrystalline Thin Film Transistors Processed with High-Pressure Water Vapor Annealing

This paper discusses electrical characteristics and trap-state density in polycrystalline silicon (poly-Si) used in bottom-gate poly-Si thin film transistors (TFTs) processed with high-pressure water vapor annealing (HWA). The threshold voltage uniformity of the HWA-processed TFTs is improved by 42% for N-channel and 38% for P-channel TFTs in terms of standard deviation, and carrier mobility is enhanced by 10% or greater for both N- and P-channel TFTs than those TFTs processed conventionally. Subthreshold swing is also improved by HWA, showing that HWA postannealing is effective for improving the Si/SiO2 interface of the bottom-gate TFTs. Two types of TFTs having different poly-Si crystallinities are examined to investigate carrier transport in poly-Si processed by HWA postannealing. The evaluation of trap-state density for the two types of poly-Si reveals that HWA postannealing is more efficient for N-channel than for P-channel TFTs. Furthermore, HWA postannealing is more effective for poly-Si with high crystallinity to improve TFT characteristics. The analysis of the trap-state distributions and the activation energy of TFT drain current indicate that HWA deactivates dangling bonds highly localized at poly-Si grain boundaries (GBs). Thus, HWA postannealing effects can be interpreted by a GB barrier potential model similar to that applied to conventional hydrogenation.