Types Of Multipliers Research Articles

Efficiency of energy-generating tiles with different types of multipliers

Problem. With the urgent need for sustainable and renewable energy solutions, the integration of energy-harvesting technologies in urban infrastructure has become a focal point of innovation. Energy-generating tiles, transforming pedestrian movement into electricity, offer a viable path forward. Yet, their efficiency hinges on the internal design, particularly the type of multipliers used. Goal. This study aims to assess and compare the efficiency of energy-generating tiles equipped with helical and straight-cut gear multipliers, to identify the optimal design for maximizing energy conversion in urban environments. Methodology. An experimental setup was created to test prototypes of the energy-generating tiles under controlled foot traffic conditions. The study measured and analyzed the electrical output and efficiency of tiles with both types of gear multipliers, simulating real pedestrian traffic scenarios. Results. Energy-generating tiles featuring straight-cut gears outperformed those with helical gears in energy output and conversion efficiency. The research also illuminated the influence of pedestrian dynamics, like step force and frequency, on tile performance. Originality. This research advances renewable energy technology by offering a comprehensive analysis of energy-generating tile efficiency with different gear multipliers. It introduces an innovative method for evaluating tile performance, underscoring the significance of gear design in energy conversion. Practical value. The findings have considerable implications for sustainable urban development, suggesting that implementing energy-generating tiles in areas with high foot traffic could significantly enhance urban renewable energy sources. This study not only guides the design of more efficient energy-harvesting tiles but also encourages their broader adoption, supporting urban sustainability goals and the reduction of carbon emissions.

ANALISIS DAMPAK EKONOMI EKOWISATA PULAU BERAS BASAH KOTA BONTANG

Beras Basah Island in Bontang City has become one of the attractions of marine ecotourism. Ecotourism activities on Beras Basah Island cause an economic impact on local communities. So this study aims to determine the economic impact of ecotourism on Beras Basah Island, Bontang City. The data analysis method used is a multiplier analysis consisting of Keynesian Local Multiplier Income, Ratio Income Multiplier Type I and Ratio Income Multiplier Type II. Based on the results of the analysis conducted, it can be concluded that the ecotourism business on Beras Basah Island has not had an impact on the local community, this can be seen in the Keynesian Income Multiplier of 0.22, the Type I Income Multiplier Ratio was recorded at 1.47 and the Type II Income Multiplier Ratio was 1.91.

Modeling the effects of power efficient approximate multipliers in radio astronomy correlators

Large scale Radio Telescopes for Radio Astronomy highly depend on the availability of large (digital) processing capacities for imaging. Estimates concerning power efficiency for future Radio Telescopes lead to anticipated power consumption numbers beyond feasibility. To reduce the power budget, the use of approximate multipliers within the correlator is explored. A baseband equivalent executable model of a radio synthesis telescope is constructed to assess the effects of approximate multipliers. Besides ideal multipliers with floating point accuracy, the use of accurate 8-bit multipliers and 4 different types of approximate multipliers is explored. For each of these multipliers, the energy efficiency of an individual multiplier is known and used to determine the energy efficiency improvement of a correlator when using approximate multipliers. The effects of approximation are quantified by 3 metrics (Signal-to-Noise-Ratio (SNR), Spurious-Free-Dynamic-Range (SFDR) and Root-Mean-Square (RMS) level) derived from maps constructed by the executable model based on an empty sky with only a single point source. This is considered to be the worst case scenario. For illustration purposes, a more realistic input is processed by the model as well. The metrics have been determined based on different SNR levels at the input of each antenna element. For input SNR levels up to 10 dB, all types of approximate multipliers used in this paper can be exploited to improve energy efficiency of correlators, leading to a maximum energy reduction of 19 %. For input SNR values up to 30 dB an energy improvement up to 12 % can be achieved. These percentages are based on implementations in a 40nm low power IC technology at 1 GHz.

High-Performance Hardware Implementation of the Saber Key Encapsulation Protocol

Information is pivotal in contemporary society, highlighting the necessity for a secure cryptographic system. The emergence of quantum algorithms and the swift advancement of specialized quantum computers will render traditional cryptography susceptible to quantum attacks in the foreseeable future. The lattice-based Saber key encapsulation protocol holds significant value in cryptographic research and practical applications. In this paper, we propose three types of polynomial multipliers for various application scenarios including lightweight Schoolbook multiplier, high-throughput multiplier based on the TMVP-Schoolbook algorithm and improved pipelined NTT multiplier. Other principal modules of Saber are designed encompassing the hash function module, sampling module and functional submodule. Based on our proposed multiplier, we implement the overall hardware circuits of the Saber key encapsulation protocol. Experimental results demonstrate that our overall hardware circuits have different advantages. Our lightweight implementation has minimal resource consumption. Our high-throughput implementation only needs 23.28 μs to complete the whole process, which is the fastest among the existing works. The throughput rate is 10,988 Kbps and the frequency is 416 MHz. Our hardware implementation based on the improved pipelined NTT multiplier achieved a good balance between area and performance. The overall frequency can reach 357 MHz.

Speed multipliers for renewable energy systems-hydro and wind

The paper main objective is to extend the library of planetary multipliers that can be used in wind turbines’ and hydro units’ applications, by taking into account the conditions of obtaining higher efficiencies and higher multipication ratios for a reduced overall dimension. The presented solutions are derived from some representative speed reducer by the flow power inversion. By means of these solutions, a comparative analysis of the structural, kinematical and dynamic specific features of different types of planetary speed multipliers is presented in the paper

Optimized Multiplier Architectures for Enhanced Performance and Efficiency in MAC Units

This paper investigated the performance of Vedic multipliers in a 32-bit Multiplier-Accumulator Unit (MAC) by comparing Urdhva Tiryakbhyam and Nikhilam Sutras with various adder architectures. The goal was to identify the optimal combination of speed and resource efficiency. Urdhva Tiryakbhyam with CLA emerged as the fastest option, achieving a minimal delay of 0.709 ns. However, this came at the cost of higher resource utilization, measured in Logic Look-Up Tables (LUTs). Conversely, Nikhilam implementations generally required fewer LUTs, making them more resource-efficient, but they exhibited slightly slower performance. CLA consistently delivered the best delay for both Vedic multiplier types among the adder architectures. All the explored configurations are viable for practical implementation on Xilinx ISE 14.7. The key takeaway is that the choice between Urdhva Tiryakbhyam and Nikhilam and the specific adder architecture hinges on the application’s priorities.

Economic Valuation of Bubohu Religious Tourism Village in Gorontalo District

The development of industrial tourism at local level directly opens up employment in tourism areas which can be managed and utilised by local communities. Bubohu religious tourism village is one of the tourism villages having a good potential economy, however there still are identified poverty issues in the village. This research calculates the value of potential economic and multiplier effect value of religious tourism village Bubohu by identifying the amount of visitor expenditure, business unit income, expenditure of business units and labour expenditure in this village. The research results obtained the average value of Willingness to Pay (WTP) indicating the expenditure of individual tourists visiting amounted to Rp 395.555/person. Then the estimated economic valuation of Bubohu religious tourism village which is based on tourist expenditure amoundted Rp 7.512.391.111. Furthermore, economic value will increase along with tourists coming to visit Bubohu religious tourism. The multiplier effect analysis results acquired that Keynesian Income Multiplier value is 1,25, and Ratio Income Multiplier type 1 is 1,45 as well as Ratio Income Multiplier type 2 is 1,87. The results indicated that the existing tourism activities at Bubohu religious tourism village have a good economic impact on the local communities.

A Multimode Wide Output Range High-Voltage Power Supply for Magnetrons

High voltage electric field power supply with a wide output voltage range is widely used in microwave generating, X-ray, ion implantation, and other fields. However, the existing high voltage power supplies cannot meet the demand of wide voltage regulation range for high-voltage high-power magnetrons. In this paper, a multi-mode high voltage DC-DC converter with a wide output voltage range is proposed, which is composed of two input series connected full-bridge inverters, six inductor – inductor – capacitor (LLC) resonant networks, and two types of voltage multipliers. The proposed high voltage power supply owns six operation modes and five available output voltage ranges by modifying the inverter's driving scheme. Thus, the proposed converter can reduce the variation range of the resonant network's gain when regulating the output voltage widely. In this paper, a detailed comparative analysis is presented of the operating principle of the proposed topology and its six operation modes. Moreover, the expression of its output voltage gain is shown with the control strategy. Finally, a 7.5kW 3.5-10kV output prototype is built to verify. The results convincingly demonstrate the applicability of the proposed converter offering high efficiency over a wide range of output power.

The dynamic effect of public debt on economic growth in the era of Macroprudential policy regime: a Bayesian approach

Purpose This study aims to test the dynamic impact of public debt and economic growth on newly democratized African countries (South Africa and Namibia) and compare the findings with those of newly democratized European countries (Germany and Ukraine) during the period 1990–2022. Design/methodology/approach The methodology involves three stages: identifying the appropriate transition variable, assessing the linearity between public debt and economic growth and selecting the order m of the transition function. The linearity test helps identify the nature of relationships between public debt and economic growth. The wild cluster bootstrap-Lagrange Multiplier test is used to evaluate the model’s appropriateness. All these tests would be executed using the Lagrange Multiplier type of test. Findings The results signify the policy switch, as the authors find that the relationship between public debt and economic growth is characterized by two transitions that symbolize that the current stage of the relationship is beyond the U-shape; however, an S-shape. The results show that for newly democratized African countries, the threshold during the first waves was 50% of GDP, represented by a U-shape, which then transits to an inverted U-shape with a threshold of 65% of GDP. Then, for the European case, it was 60% of GDP, which is now 72% of GDP. Originality/value The findings suggest that an escalating level of public debt has a negative impact on economic growth; therefore, it is important to implement fiscal discipline, prioritize government spending and reduce reliance on debt financing. This can be achieved by focusing on revenue generation, implementing effective taxation policies, reducing wasteful expenditures and promoting investment and productivity-enhancing measures.

Why Economic Growth Stimulates More Growth in Some Countries Rather than Others

Leontief multipliers are an important component of economic growth. However, input–output analysis is generally treated as a methodological tool for studying other questions in development. The size of multipliers themselves is of interest, as they determine how much nations benefit economically from the growth of base industries. Of the three types of multipliers—industrial supply purchases by firms, consumer goods purchases by workers, and growth derived from all sources—only the first has attracted attention in the global value chain literature; the other two have been neglected. We use OECD data on a large sample of nations in 2005, 2010, and 2015 to show that significant cross-national and inter-industrial differences exist in the size of multipliers. Contrary to expectations, higher-income countries can sometimes have lower multipliers than lower-income countries. The largest multipliers tend to be in the global South. We then provide a model explaining the differences in multipliers in terms of the domesticity of purchases, the wage intensity of production, the geographical size of the country, and the changing roles of GDP per capita and education as societies develop. The significance of these findings for development policy is discussed.

FPGA implementation of proficient Vedic multiplier architecture using hybrid carry select adder

ABSTRACT Nowadays, the application of computations and communications is needed for high performance, reduced size and lower power utilisation. The multiply and add functions are one of the frequently used operations in digital signal processing. Various types of multipliers are available in digital Various types of multipliers are available for various Signal processing applications.. Among these multipliers, Vedic multiplier is one of the most optimised multipliers used in a signal processing module. In the existing method, the Vedic multiplier is designed with conventional adders, which is having higher area utilisation, lower speed and higher power consumption. Hence, the modified Vedic multiplier is proposed to improve the speed of multiplication using hybrid technology. The partial products of the proposed multiplication are added using 2 × 2 Vedic multiplier and hybrid carry select adder (binary to excess one converter (BEC), Han-Carlson adder and Multiplexer). The critical path delays of hybrid 4 × 4 Vedic multiplier are the summation of 2 × 2 Vedic multiplier, two full adders, two multiplexers and two BECs for producing the final product. The proposed hybrid Vedic multiplier is operated at high speed with reduced size as compared to the existing multiplier techniques. The proposed hybrid Vedic multiplier is designed and simulated using Verilog HDL and implemented in Spartan 6 field-programmable gate array device. The implementation results showed that the delay of the proposed multiplier gets ameliorated as compared to array multiplication (30.84%), Wallace tree multiplication (29.52%), multiplication based on compressor (23.71%), Vedic multiplication by carry look-ahead adder (22.91%), Vedic multiplication by ripple carry adder (14.45%), revised booth multiplication (15.42%) and Vedic multiplication by Han-Carlson adder with BEC (13.95%) and hybrid multiplier (11.37%).

Low-Power Very-Large-Scale Integration Implementation of Fault-Tolerant Parallel Real Fast Fourier Transform Architectures Using Error Correction Codes and Algorithm-Based Fault-Tolerant Techniques

As technology advances, electronic circuits are more vulnerable to errors. Soft errors are one among them that causes the degradation of a circuit’s reliability. In many applications, protecting critical modules is of main concern. One such module is Fast Fourier Transform (FFT). Real FFT (RFFT) is a memory-based FFT architecture. RFFT architecture can be optimized by its processing element through employing several types of adder and multipliers and an optimized memory usage. It has been seen that various blocks operate simultaneously in many applications. For the protection of parallel FFTs using conventional Error Correction Codes (ECCs), algorithmic-based fault tolerance (ABFT) techniques like Parseval checks and its combination are seen. In this brief, the protection schemes are applied to the single RAM-based parallel RFFTs and dual RAM-based parallel RFFTs. This work is implemented on platforms such as field programmable gate arrays (FPGAs) using Verilog HDL and on application-specific integrated circuit (ASIC) using a cadence encounter digital IC implementation tool. The synthesis results, including LUTs, slices registers, LUT–Flip-Flop pairs, and the frequency of two types of protected parallel RFFTs, are analyzed, along with the existing FFTs. The two proposed architectures with the combined protection scheme Parity-SOS-ECC present an 88% and 33% reduction in area overhead when compared to the existing parallel RFFTs. The performance metrics like area, power, delay, and power delay product (PDP) in an ASIC of 45 nm and 90 nm technology are evaluated, and the proposed single RAM-based parallel RFFTs architecture presents a 62.93% and 57.56% improvement of PDP in 45 nm technology and a 67.20% and 60.31% improvement of PDP in 90 nm technology compared to the dual RAM-based parallel RFFTs and the existing architecture, respectively.

The Impact of Marine Ecotourism Development in Rupat Island Indonesia

The tourism sector has made considerable contributions to the realization of economic equality, especially among the community living in coastal areas who are highly dependent on marine resources. This research was conducted in July 2022 in the marine ecotourism area of Rupat Island, Riau Province to analyze the impact of developing marine ecotourism on Rupat Island. Primary and secondary data collected through surveys were analyzed using the multiplier effect analysis. The results of the analysis resulted in a Keynesian Income Multiplier value of 1.03, indicating an increase in the income of workers and business owners in the marine ecotourism area of Rupat Island. The increase was to be 1.03 rupiah and with Income Multiplier Type I ratio of 1.07 and Type II ratio of 1.09. It can be taken into conclusion that the tourism activities on Rupat Island bring effects on the local community.

Design and Optimization of 4-Bit Array Multiplier with Adiabatic Logic Using 65 nm CMOS Technologies

ABSTRACT This paper proposes a 4-bit array multiplier useful in the design of basically mixer circuit, which is highly involved in signal and image processing using an efficient low-power VLSI technique. The presented architecture is completely implemented adiabatic techniques in the Near Threshold Region, which optimize the product of propagation delay and power dissipation. Multiplier is the most frequently used element in many digital electronics applications. Depending on the applications, various types of multipliers emerge. With this technique, the total power dissipation, i.e. dynamic power dissipation as well as static power dissipation is less as compared to the conventional CMOS technique. The Near Threshold Adiabatic Logic (NTAL) technique is used with a single timevarying power supply which reduces the clock tree management and enhances the energy-saving capability. Simulation of the proposed design is done by Cadence virtuoso schematic editor with specter simulator on TSMC 65 nm technology node to verify the optimized result. Also comparing our result to conventional CMOS techniques with all the same design parameters, the result shows that power dissipation improvement of approximately 66.6%, 14.4%, and 64.6% with respect to varying frequency, supply voltage, and load capacitance with other parameters keep constant such as if the frequency is varying than capacitance load value is C load = 10 pF and V DD(max) = 1.2 V, similarly if the supply voltage is varying than capacitance load value is C load = 10 pF and frequency F = 4 GHz and if load capacitance is varying than frequency F = 4 GHz and supply voltage V DD(max) = 1.2 V.

EAM: Ensemble of approximate multipliers for robust DNNs

Deep neural networks (DNNs) are one of the most prominent technologies of our time, as they achieve state-of-the-art performance in a wide range of real-world applications such as healthcare, online banking, etc. However, recent advances in deep learning have opened up a largely unexplored surface for adversarial attacks, jeopardizing the integrity of DNN systems. DNNs are vulnerable to adversarial samples that are generated by perturbing correctly classified inputs to cause DNN models to mispredict. This can potentially lead to catastrophic consequences, especially in critical and security-sensitive applications such as autonomous driving and video surveillance systems.We propose ensemble of approximate multipliers (EAM), an architectural technique that uses a combination of approximate multipliers to protect DNNs against adversarial attacks. Approximate computing is known for its effectiveness in improving the energy-efficiency of computing platforms at the cost of slight accuracy loss. Using approximation in the form of inexact multipliers is also effective for increasing robustness by injecting input-dependent noises into the outputs of DNNs. However, resiliency of DNNs against malicious attacks depends on the type of an approximate multiplier. Based on level of approximation, robustness of DNNs changes by a large margin. We exploit this variability and propose using an ensemble of different types of approximate multipliers. EAM increases robustness across a wide range of attack scenarios. In particular, we show that successful attacks against an exact DNN have poor transferability to EAM. The transferability is also poor for a black-box model where perturbed inputs are generated by a substitute model. In addition, EAM is resilient against a white-box attack scenario where an attacker has full knowledge of approximate hardware. Our ensemble technique does not require duplication of computing cores nor memory units. EAM only uses additional approximate compressors within the original multipliers. We conduct extensive experiments on a set of strong adversarial attacks. We empirically show that EAM increases robustness over the exact model with negligible impact on accuracy of benign inputs.

The use of comparative market coefficients to measure office property market and fair values: Some special aspects

Subject. This article deals with the issues of assessing the market value of office real estate. Objectives. The article aims to substantiate the need to use special calculated values of multipliers differentiated by the main cost factors. Methods. The study is based on the verification of the considered methods of valuation of office real estate on the basis of pair and multiple regression methods, as well as the theoretical and methodological aspects of assessing the value of office real estate, in particular, on the application of the gross rent multiplier (GRM) method. We also used general scientific methods of cognition, empirical and economic analysis methods, methods of scientific abstraction, comparison, classification, generalization, grouping, and graphic analysis. Results. The article identifies the main factors in determining the value of office real estate, analyzes the values of the office real estate objects’ value by published multipliers and various calculated types of multipliers, and also it compares the values obtained. It focuses on the fact that the value of office real estate obtained on the basis of published values of gross rent multipliers, is underestimated. The article also justifies the need to use multipliers that are more detailed in terms of cost factors.

An Adaptive Lagrangian-Based Scheme for Nonconvex Composite Optimization

This paper develops a novel adaptive, augmented, Lagrangian-based method to address the comprehensive class of nonsmooth, nonconvex models with a nonlinear, functional composite structure in the objective. The proposed method uses an adaptive mechanism for the update of the feasibility penalizing elements, essentially turning our multiplier type method into a simple alternating minimization procedure based on the augmented Lagrangian function from some iteration onward. This allows us to avoid the restrictive and, until now, mandatory surjectivity-type assumptions on the model. We establish the iteration complexity of the proposed scheme to reach an ε-critical point. Moreover, we prove that the limit point of every bounded sequence generated by a procedure that employs the method with strictly decreasing levels of precision is a critical point of the problem. Our approach provides novel results even in the simpler composite linear model, in which the surjectivity of the linear operator is a baseline assumption. Funding: N. Hallak’s research was partially supported by the Israel Science Foundation [Grant 637/21]. M. Teboulle’s research was partially supported by the Israel Science Foundation [Grants 1844-16 and 2619-20].

A Sweeping Process Control Problem Subject To Mixed Constraints

In this study, we investigate optimal control problems that involve sweeping processes with a drift term and mixed inequality constraints. Our goal is to establish necessary optimality conditions for these problems. We address the challenges that arise due to the combination of sweeping processes and inequality mixed constraints in two contexts: regular and non-regular. This requires working with different types of multipliers, such as finite positive Radon measures for the sweeping term and integrable functions for regular mixed constraints. For non-regular mixed constraints, the multipliers correspond to purely finitely additive set functions.

A Review of Vedic Mathematics for the Design of High-Speed Arithmetic RISC Processors

Vedic Mathematics is a collection of techniques and concepts developed from ancient Indian mathematical books known as the Vedas. These strategies are designed to make different mathematical computations easier and faster. High-throughput RISC Processor Design, on the other hand, includes the creation of processors that prioritize the execution of a high number of instructions per unit of time. If there have been breakthroughs relating to Vedic Mathematics and High-Throughput RISC Processor Design, it would be intriguing to investigate how these old mathematical ideas may be utilized to improve the efficiency of current processor designs. Give a summary of the work, stressing the potential benefits and drawbacks of incorporating Vedic Mathematics concepts into the design of High-Throughput RISC computers. Introduce Vedic Mathematics and High-Throughput RISC Processor Design separately. Explain briefly why you're looking at incorporating Vedic Mathematics into CPU architecture. Outline key Vedic Mathematics concepts that may be applied to processor design. What distinguishes these ideas from typical mathematical approaches Provide an overview of the fundamental ideas and issues involved in the design of high-throughput RISC processors. Emphasize the critical areas for improvement and integrating principles from Vedic Mathematics into Processor Architecture: Investigate the use of Vedic Mathematics principles in processor architecture to discuss how these concepts may be utilized to solve specific problems or improve aspects of high-throughput RISC architectures. The importance of multipliers in Arithmetic Unit performance is underlined. The incorporation of Vedic Science, an ancient mathematical system comprised of 16 Sutras, implies a fresh method for arithmetic computations. The suggestion comprises optimizing the Vedic multiplier type Urdhva Triyakbhyam by substituting Convey Save Viper for the usual carry. This is done to reduce delays caused by standard adders and incomplete products aspire to outperform traditional designs in terms of speed. The explicit data on the speed gains is obtained and how they were assessed will bolster the claims and utilization of the proposed proficient Vedic multiplier in the number juggling module of the RISC processor. In addition, stating its application in the field of digital signal processing (DSP) broadens the scope of work. Validation of RTLs and FPGAs for the Register-Transfer Level (RTL) implementation of the proposed Math Unit in VHDL, paired with simulation using Xilinx ISE EDA tools, is a useful step in verifying the design. Validation on an FPGA device, especially a Vertex-IV, provides credibility to the suggested solution.

DAMPAK WISATA PANTAI MINANGA TERHADAP EKONOMI LOKAL MASYARAKAT DESA KOTAJIN UTARA KABUPATEN GORONTALO UTARA

Coastal tourism is progressing rapidly along with the development of digital technology, especially the development of social media. Various information on newly opened beach tourism locations was introduced on social media, thereby attracting tourists to visit and ultimately opening up business opportunities for local communities in tourist areas. This study aims to determine the impact of Minanga Beach tourism on the people's economy of Kotajin Utara Village. A total of 99 tourist respondents, 32 business unit owners, and 24 workers were interviewed to see the impact of tourism on the community's local economy. Keynesian Income Multiplier and Multiplier analyses were used to determine the direct, indirect, and continued impact of Minanga beach tourism. The results showed that Minanga Beach tourism had an impact on the local economy of the people of Kotajin Utara Village, Atinggola District, Gorontalo Utara Regency, with the Keynesian Income Multiplier value of 1.77, Ratio of Income Multiplier Type I of 1.13, and Ratio of Income Multiplier Type II of 1.70.